Frameworks for Interconnect Optimization
The electrical interconnections in a VLSI system are represented by the geometrical layout of metal layers in a chip. This layout is the result of a complex engineering process, which often involves manual design and automatic layout generation tools, as outlined in Chap. 2. In typical design scenarios, the generated interconnect layout needs to be revised and refined by several iterative steps of checking and optimization. These iterations are necessary since not all the relevant performance parameters and figures-of-merit of the circuit have been considered in the initial layout generation steps. In many cases, the initial layout generation attempts to minimize circuit area and total wire length. The most common cycle of revisions involves circuit timing, as wire delay on certain nets exceeds early estimates, and changes are required to speed-up the critical paths in the circuit. Similar checking and fixing is required with regard to cross-talk noise. It is also possible to optimize the layout in order to reduce power dissipation, or improve manufacturability (e.g., by increasing spacing between wires where appropriate) [Chiluviri 95]. An interesting design scenario that requires layout optimization is, where an existing design is transferred to a newer technology with a new set of geometrical design rules. In many cases it makes sense to take a given area, allocated for a set of wires, as a fixed constraint. This is very practical as it allows independent treatment of separate slices of layout with almost no impact of each slice on the other slices. Optimization of the wires in this area may involve changing the widths of the wires and spaces between them (while keeping their basic topology unchanged), or even more significant changes such as reordering (rearranging) of the wires.