Scaling Dependent Electrical Modeling of Interconnects

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer


From the early days of MOS devices, the miniaturization of device sizes in each generation of process technology has been the main driver of improvements in VLSI circuits. As such, photolithography was improved in each generation so that a chip’s area could be shrunk by approximately half through the migration of a product to a new process technology. This corresponds to uniform downscaling of all linear dimensions, such as device length and width, by a factor of \( 1/\sqrt{2} \). Ideal scaling theory, or constant-field scaling, has been described by [Dennard 74], in which it is assumed that both lateral and vertical dimensions are made smaller by a factor of 1/ S (where S > 1 with the classical choice \( S\approx \sqrt{2} \)) and all voltages are scaled by 1/ S. Ideal scaling provides a smaller circuit area that results in reduced manufacturing cost and in shorter delays, leading to better circuit performance and lower power dissipation.


Wire Length Wire Resistance Center Wire Delay Change Technology Scaling 
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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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