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Interconnect Aspects in Design Methodology and EDA Tools

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer
Chapter

Abstract

The physical layout of a VLSI system is usually represented at a high level of abstraction as a chip-plan, also called a “floor plan”. As described in [Cong 01], the first step in planning is to generate a , which defines the global, semi-global, and local wires. This step is necessary because systems are often defined initially as a , where blocks are clustered together according to functional behavior, while physical distances and geometrical relationships are ignored. A logical hierarchy only represents the nesting of functional blocks in the high-level architectural description (see Fig. 2.1). A physical hierarchy is better in mapping onto a two-dimensional layout surface than is a simple logical hierarchy because it considers wires and physical sizes. In the physical hierarchy, connections between the different blocks obtained from top-level partitioning are the global interconnects, and the connections between different modules within the same block are semi-global or local.

References

  1. [Cong 01]
    Cong, Jason. “An interconnect-centric design flow for nanometer technologies.”Proceedings of the IEEE 89.4 (2001): 505–528.Google Scholar
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    Cong, Jason, et al. “Performance optimization of VLSI interconnect layout.”Integration, the VLSI journal 21.1 (1996): 1–94.Google Scholar
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    W. J. Dally and A. Chang, “The Role of Custom Design in ASIC Chips,” in Proc. Design Automation Conf., Jun. 2000, pp. 643–647.Google Scholar
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    D. Pandini, L. T. Pileggi, and A. J. Strojwas, “Congestion-Aware Logic Synthesis,” in Proc. DATE, Mar. 2002, pp. 664–671.Google Scholar
  5. [Sherwani 95]
    Sherwani, Naveed A. Algorithms for VLSI physical design automation. Kluwer Academic Publishers, 1995.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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