Interconnect Aspects in Design Methodology and EDA Tools
The physical layout of a VLSI system is usually represented at a high level of abstraction as a chip-plan, also called a “floor plan”. As described in [Cong 01], the first step in planning is to generate a , which defines the global, semi-global, and local wires. This step is necessary because systems are often defined initially as a , where blocks are clustered together according to functional behavior, while physical distances and geometrical relationships are ignored. A logical hierarchy only represents the nesting of functional blocks in the high-level architectural description (see Fig. 2.1). A physical hierarchy is better in mapping onto a two-dimensional layout surface than is a simple logical hierarchy because it considers wires and physical sizes. In the physical hierarchy, connections between the different blocks obtained from top-level partitioning are the global interconnects, and the connections between different modules within the same block are semi-global or local.
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