An Overview of the VLSI Interconnect Problem

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer


VLSI interconnect issues are addressed in this book from a design viewpoint, focusing primarily on the layout of metal wires in digital integrated circuits. Our goal is the optimization of wire structures under various constraints imposed by system specifications and by physical limitations. The objectives of this chapter are to provide an introduction to the evolution of interconnect design problem, to present the motivation for using multinet optimization approaches, and to give the reader a general perspective for the rest of this book.


Metal Layer Gate Delay Circuit Architecture Wire Delay Adjacent Wire 
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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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