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An Overview of the VLSI Interconnect Problem

  • Konstantin Moiseev
  • Avinoam Kolodny
  • Shmuel Wimer
Chapter

Abstract

VLSI interconnect issues are addressed in this book from a design viewpoint, focusing primarily on the layout of metal wires in digital integrated circuits. Our goal is the optimization of wire structures under various constraints imposed by system specifications and by physical limitations. The objectives of this chapter are to provide an introduction to the evolution of interconnect design problem, to present the motivation for using multinet optimization approaches, and to give the reader a general perspective for the rest of this book.

Keywords

Metal Layer Gate Delay Circuit Architecture Wire Delay Adjacent Wire 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. [Bakoglu 85]
    Bakoglu, H. B., and James D. Meindl. "Optimal interconnection circuits for VLSI." Electron Devices, IEEE Transactions on 32.5 (1985): 903–909.CrossRefGoogle Scholar
  2. [Bohr 95]
    M. T. Bohr, “Interconnect scaling – the real limiter to high performance ULSI,” 1995, in IEDM, pp. 241–244.Google Scholar
  3. [Bolotin 04]
    Bolotin, Evgeny, et al. “QNoC: QoS architecture and design process for network on chip.” Journal of Systems Architecture 50.2 (2004): 105–128.CrossRefMathSciNetGoogle Scholar
  4. [Christie 00]
    Christie, P.; Stroobandt, D., “The interpretation and application of Rent's rule,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol. 8, no. 6, pp. 639–648, Dec. 2000. doi: 10.1109/92.902258Google Scholar
  5. [Davis 03]
    Jeffrey A. Davis and James D. Meindl. 2003. Interconnect Technology and Design for Gigascale Integration. Kluwer Academic Publishers, Norwell, MA, USA.CrossRefzbMATHGoogle Scholar
  6. [Dennard 74]
    R. Dennard “Design of ion-implanted MOSFETs with very small physical dimensions”, IEEE Journal of Solid State Circuits, vol. SC-9, no. 5, pp. 256–268, 1974CrossRefGoogle Scholar
  7. [Enright 09]
    Enright, J. N. D., & Peh, L.-S. (2009). On-chip networks. San Rafael, Calif.: Morgan & Claypool Publishers.Google Scholar
  8. [Magen 04]
    N. Magen, A. Kolodny, U. Weiser and N. Shamir, “Interconnect power dissipation in a microprocessor”, International Workshop on System Level Interconnect Prediction, pp. 7–13, 2004.Google Scholar
  9. [Moore 65]
    Moore, Gordon E. "Cramming More Components onto Integrated Circuits." Electronics, April 19, 1965, 38(8), pp. 114–17.Google Scholar
  10. [Shacham 09]
    Shacham-Diamand, Y. (Ed.). (2009). Advanced nanoscale ULSI interconnects: fundamentals and applications. Springer.Google Scholar
  11. [Stroobandt 01]
    Dirk Stroobandt. 2001. A priori system-level interconnect prediction: Rent's rule and wire length distribution models. In Proceedings of the 2001 international workshop on System-level interconnect prediction (SLIP '01). ACM, New York, NY, USA, 3–21. DOI=10.1145/368640.368645 http://doi.acm.org/10.1145/368640.368645Google Scholar
  12. [Sylvester 98]
    D. Sylvester and K. Keutzer, “Getting to the bottom of deep submicron”, Proc. ICCAD, pp. 203–211, 1998.Google Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Konstantin Moiseev
    • 1
  • Avinoam Kolodny
    • 2
  • Shmuel Wimer
    • 3
  1. 1.IntelHaifaIsrael
  2. 2.TechnionHaifaIsrael
  3. 3.Bar-Ilan UniversityRamat-GanIsrael

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