Concluding Remarks

  • Érika Cota
  • Alexandre de Morais Amory
  • Marcelo Soares Lubaszewski


About a decade ago, networks-on-chip emerged from a potential solution for the intra-chip communication problems arising in complex systems (Guerrier and Greiner 2000), to a major research topic with its specific conferences (NoCs 2011; NoCArch 2011) and then to an industrial reality (Karim et al. 2002; Goossens et al. 2005). A huge amount of works have been proposed on design oriented features of NoCs, creating equally large NoC design diversity (Bjerregaard and Mahadevan 2006). Nevertheless, efficient test and reliability approaches are required to turn NoC-based systems into a consolidated industry reality and to achieve much more challenging designs such as many-core systems. As a matter of fact, a considerable amount of effort has been made towards an economically viable, testable, and reliable NoC-based system. The increasing interest in the topic has motivated the writing of this book, where we have put together and organized such large amount of material, summarizing the most relevant scientific contributions, and identifying some open issues. The final chapter of this book addresses the open issues.


  1. Amory AM, Goossens K, Marinissen EJ, Lubaszewski M, Moraes F (2007) Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism. IET Comput Digit Tech 1(3):197–206CrossRefGoogle Scholar
  2. Amory AM, Lazzari C, Lubaszewski M, Moraes F (2010) A new test scheduling algorithm based on networks-on-chip as test access mechanism. J Parallel Distr Com 71(5):675–686CrossRefGoogle Scholar
  3. Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Comput Surv 38:1–51CrossRefGoogle Scholar
  4. Borkar S (2007) Thousand core chips: a technology perspective. In: Proceedings of the design automation conference (DAC), San Diego, California, pp 746–749Google Scholar
  5. Brière M, Girodias B, Bouchebaba Y, Nicolescu G, Mieyeville F, Gaffiot F, O’Connor I (2007) System level assessment of an optical NoC in an MPSoC platform. In: Proceedings of the design, automation and test in Europe conference (DATE), Nice, France, pp 1084–1089Google Scholar
  6. Chan M-J, Hsu C-L (2010) A strategy for interconnect testing in stacked mesh network-on-chip. In: Proceedings of the defect and fault tolerance in VLSI systems (DFT), Kyoto, Japan, pp 122–128Google Scholar
  7. Cota E, Liu C (2006) Constraint-driven test scheduling for NoC-based systems. IEEE Transactions on CAD 25(11):2465–2478Google Scholar
  8. Cota E, Carro L, Lubaszewski M (2004) Reusing an on-chip network for the test of core-based systems. ACM Trans Des Autom Electron Syst 9(4):471–499CrossRefGoogle Scholar
  9. Feero BS, Pande PP (2009) Networks-on-chip in a three-dimensional environment: a performance evaluation. IEEE Trans Comput 58(1):32–45Google Scholar
  10. Goel SK, Marinissen EJ, Nguyen T, Oostdijk S (2004) Test infrastructure design for the Nexperia home platform PNX8550 system chip. In: Proceedings of the design, automation, and test in Europe (DATE), Paris, France, pp 108–113Google Scholar
  11. Goossens K, Dielissen J, Radulescu A (2005) Æthereal network on chip: cixconcepts, architectures and implementations. IEEE Des Test Comput 22(5):414–421CrossRefGoogle Scholar
  12. Guerrier P, Greiner A (2000) A generic architecture for on-chip packet-switched interconnections. In: Proceedings of the design automation and test in Europe (DATE), Paris, France, pp 250–256Google Scholar
  13. Hervé M, Almeida P, Kastensmidt FL, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proceedings of the Latin American test workshop (LATW). Punta del Este, UruguayGoogle Scholar
  14. Hussin AF, Yoneda T, Fujiwara H (2007) Optimization of NoC wrapper design under bandwidth and test time constraints. In: Proceedings of the European test symposium (ETS), Freiburg, Germany, pp 35–42Google Scholar
  15. Karim F, Nguyen A, Dey S (2002) An interconnect architecture for networking systems on chips. IEEE Micro 22(5):36–45CrossRefGoogle Scholar
  16. NoCArc. Workshop on network-on-chip architectures. Accessed 23 June 2011
  17. NoCs. International symposium on networks-on-chip. Accessed 23 June 2011
  18. Pavlidis VF, Friedman EG (2007) 3-D topologies for networks-on-chip. IEEE T VLSI Syst 15(10):1081–1090CrossRefGoogle Scholar
  19. Pontes J, Moreira M, Moraes F, Calazans N (2011) Hermes-A: an asynchronous NoC router with distributed routing. In: Proceedings of the international conference on power and timing modeling, optimization and simulation (PATMOS), Grenoble, France, pp 150–159Google Scholar
  20. Raik J, Govind V, Ubar R (2009) Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput Digit Tech 3(5):476–486CrossRefGoogle Scholar
  21. Shacham A, Bergman K, Carloni LP (2008) Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans Comput 57(9):1246–1260MathSciNetCrossRefGoogle Scholar
  22. Tran XT, Thonnart Y, Durupt J, Beroulle V, Robach C (2009) Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput Digit Tech 3(5):487–500CrossRefGoogle Scholar
  23. Xu Q, Yuan F, Huang L (2008) Re-examining the use of network-on-chip as test access mechanism. In: Proceedings of the design, automation, and test in Europe (DATE), Munich, Germany, pp 808–811Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Érika Cota
    • 1
  • Alexandre de Morais Amory
    • 2
  • Marcelo Soares Lubaszewski
    • 3
  1. 1.Instituto de InformáticaPorto AlegreBrazil
  2. 2.PUCRS – Faculdade de InformáticaHardware Design Support Group (GAPH)Porto AlegreBrazil
  3. 3.Estrada João de Oliveira RemiãoCEITEC SAPorto AlegreBrazil

Personalised recommendations