Abstract
For sub-90 nm technologies, mismatch in transistor is one of the primary obstacles to reach a high yield rate for analog designs. For example, mismatch of CMOS devices nearly doubles for every process generation less than 90 nm [80, 104] due to an inverse-square-root-law dependence with the transistor area.
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Shen, R., Tan, S.XD., Yu, H. (2012). Stochastic Analog Mismatch Analysis. In: Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0788-1_15
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DOI: https://doi.org/10.1007/978-1-4614-0788-1_15
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