• Ruijing Shen
  • Sheldon X.-D. Tan
  • Hao Yu


As VLSI technology scales into the nanometer regime, chip design engineering faces several challenges in maintaining historical rates of performance improvement and capacity increase with CMOS technologies. One profound change in the chip design business is that engineers cannot put the design precisely into the silicon chips. Chip performance, manufacture yield, and lifetime become unpredictable at the design stage, and they cannot be determined accurately at the design stage. The main culprit is that many chip parameters—such as oxide thickness due to chemical and mechanical polish (CMP) and impurity density from doping fluctuations—cannot be determined precisely and thus are unpredictable. The so-called manufacture process variations start to play a big role, and their influence on the chip’s performance, yield, and reliability becomes significant [16, 7, 170, 121, 122].


Covariance ETBR 


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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Ruijing Shen
    • 1
  • Sheldon X.-D. Tan
    • 1
  • Hao Yu
    • 2
  1. 1.Department of Electrical EngineeringUniversity of CaliforniaRiversideUSA
  2. 2.Department of Electrical and ElectronicNanyang Technological UniversitySingaporeSingapore

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