Abstract
In real hardware, the sequential logic is activated on clock edges, whereas combinational logic is constantly changing when any inputs change. All this parallel activity is simulated in Verilog RTL using initial and always blocks, plus the occasional gate and continuous assignment statement. To stimulate and check these blocks, your testbench uses many threads of execution, all running in parallel. Most blocks in your testbench environment are modeled with a transactor and run in their own thread.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
1 The SystemVerilog LRM uses “thread” and “process” interchangeably. The term “process” is most commonly associated with Unix processes, in which each contains a program running in its own memory space. Threads are lightweight processes that may share common code and memory, and consume far fewer resources than a typical process. This book uses the term “thread.” However, “interprocess communication” is such a common term that it is used in this book.
- 2.
2 This behavior is different from the VMM channel. If you set a channel’s full level to 1, the very first call to put() places the transaction in the channel, but does not return until the transaction is removed.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Spear, C., Tumbush, G. (2012). Threads and Interprocess Communication. In: SystemVerilog for Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0715-7_7
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0715-7_7
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4614-0714-0
Online ISBN: 978-1-4614-0715-7
eBook Packages: EngineeringEngineering (R0)