Abstract
CMOS transistors have been scaling exponentially in the past two decades and the intrinsic device performance has followed a commensurate scaling trend. Prior to the 90-nm node, mere shrinking of the device dimensions, following Dennard’s scaling theory, was sufficient to guarantee increased device performance; beyond the 90-nm node, new innovations were necessary to continue the historical performance scaling trend. Strain engineering and high-k/metal gate technologies were the two major innovations that made the commensurate performance scaling in the past decade possible. However, it appears that new device structures and performance boosters will continue to be the need of the future. This chapter provides a basic overview of MOSFET scaling trend, followed by a discussion of MOSFET operation in deca-nanometer scale based on the so-called virtual source injection model. A simple analytical model for transistor I–V characteristics and intrinsic transistor delay is provided and used to quantify the historical trends of MOSFET performance scaling. Carrier velocity is shown to be the main driver for the continued MOSFET performance increase. Finally, the prospect of velocity increase is reviewed for strained Si, Ge, and compound semiconductors.
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Notes
- 1.
Note that the definition of the threshold voltage is somewhat arbitrary as the transition from off-state to on-state, also known as strong inversion, is gradual. The transition region is often called weak inversion. Several definitions for the threshold voltage are given in the literature. The two most common definitions that are based on the I–V characteristics of the transistor are (1) constant current threshold voltage, where V T is defined as the gate voltage at which the drain current is equal to an empirically-defined current, usually around 10-7 A/WL, with W and L being the gate width and length in micrometer, respectively, and (2) extrapolated threshold voltage, obtained by drawing the tangent to the I–V curve at the point where the transconductance is maximum and finding the intercept with the x-axis.
References
R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. Leo Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. 9, pp. 256–268, 1974.
F. Boeuf, et al., “0.248 μm2 and 0.334 μm2 conventional bulk 6 T-SRAM bit-cells for 45 nm node low cost - general purpose applications,” in Symp. VLSI Tech., pp. 130–131, 2005.
A. Khakifirooz and D. A. Antoniadis, “MOSFET performance scaling – Part I: Historical trends,” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1391–1400, 2008.
A. Khakifirooz and D. A. Antoniadis, “MOSFET Performance scaling – Part II: Future directions,” IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1401–1408, 2008.
A. Khakifirooz, O.M. Nayfeh, and D.A. Antoniadis, “A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters,” IEEE Trans. Electron Devices, vol. 56, no. 8, pp. 1674–1680, 2008.
M. H. Na, E. J. Nowak, W. Haensch, and J. Cai, “The effective drive current in CMOS inverters,” in IEDM Tech. Dig., Dec. 2002, pp. 121–124.
M. Lundstrom, “On the mobility versus drain current relation for a nanoscale MOSFET,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 293–295, 2001.
T. Irisawa, T. Numata, T. Tezuka, N. Sugiyama, and S. Takagi, “Electron transport properties of ultrathin-body and tri-gate SOI nMOSFETs with biaxial and uniaxial strain,” in IEDM Tech. Dig., 2006, pp. 457–460.
P. Hashemi, L. Gomez, M. Canonico, and J.L. Hoyt, “Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs,” in IEDM Tech. Dig., 2008, pp. 865–868.
K. Maitra, A. Khakifirooz, P. Kulkarni, et al., “Aggressively scaled strained-silicon-on-insulator undoped-body high-k/metal-gate nFinFETs for high-performance logic applications,” IEEE Electron Device Lett., vol. 32, no. 6, pp. 713–715, 2011.
S. Narasimha, et al., “High performance 45 nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography,” in IEDM Tech. Dig., 2006, p. 689.
B. Yang, et al., “Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current,” in Symp. VLSI Tech., 2007, pp. 126–127.
D.-H. Kim and J. A. del Alamo, “Logic Performance of 40 nm InAs HEMTs,” in IEDM Tech. Dig., 2007, p. 629.
D.-H. Kim and J. del Alamo, “30 nm E-mode InAs PHEMTs for THz and future logic applications,” in IEDM Tech. Dig., 2008, p. 30.1.1.
G. G. Dewey, M. K. Hudait, K. Lee, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit, and R. Chau, “Carrier transport in high-mobility III–V quantum-well transistors and performance impact for high-speed low-power logic applications,” IEEE Electron Device Lett., vol. 29, no. 10, pp. 1094–1097, 2008.
D. Kim, T. Krishnamohan, H.S.P. Wong, and K.C. Saraswat, “Band to band tunneling study in high mobility materials : III-V, Si, Ge and strained SiGe,” in Device Research Conf., 2007, p. 57.
K. D. Cantley, Y. Liu, H. S. Pal, T. Low, S. S. Ahmed, and M. S. Lundstrom, “Performance analysis of III-V materials in a double-gate nano-MOSFET,” in IEDM Tech. Dig., 2007, p. 113.
Further Reading
Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2nd Ed., 2009.
D.K. Schroder, Semiconductor Material and Device Characterization, John Wiley and Sons, 3rd Ed., 2006.
M. Lundstrom, Fundamentals of Carrier Transport, Cambridge University Press, 2000.
S. Datta, Electronic Transport in Mesoscopic Systems, Cambridge University Press, 1997.
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Khakifirooz, A., Antoniadis, D.A. (2012). CMOS Performance Scaling. In: Murali, R. (eds) Graphene Nanoelectronics. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0548-1_1
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