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Frequency Division and Quadrature Signal Generation at Microwave Frequencies

  • Mohammed Farazian
  • Prasad S Gudem
  • Lawrence  E. Larson
Chapter

Abstract

In many receiver and transmitter architecture, or in general any application that requires frequency translation, the availability of multiple phases of a carrier frequency is desired and makes the on-chip implementation of that architecture feasible or simpler. An example is an image-reject receiver using the Hartley or Weaver architectures, where quadrature phases of the carrier signal are needed.

Keywords

Phase Noise Frequency Divider Quadrature Phase Carrier Signal Delay Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Razavi B (1998), Architectures and circuits for RF CMOS receivers. In: Proceedings of the IEEE custom integrated circuits conference, pp 393–400, May 1998Google Scholar
  2. 2.
    Yamamoto K, Fujishima M (2006) 70 GHz CMOS harmonic injection-locked divider. In: IEEE ISSCC digest of technical papers, pp 2472–2481, Feb 2006Google Scholar
  3. 3.
    Razavi B (2007) Heterodyne phase locking: a technique for high-frequency division. In: IEEE ISSCC digest of technical papers, pp 428–429, Feb 2007Google Scholar
  4. 4.
    von Buren G, Kromer C, Ellinger F, Huber A, Schmatz M, Jackel H (2006) A combined dynamic and static frequency divider for a 40 GHz PLL in 80 nm CMOS. In: IEEE ISSCC digest of technical papers, pp 2462–2471, Feb 2006Google Scholar
  5. 5.
    Lee T (2004) The Design of CMOS radio-frequency integrated circuits. Cambridge University Press, CambridgeGoogle Scholar
  6. 6.
    Mirzaei A, Heidari M, Bagheri R, Abidi A (2008) Multi-phase injection widens lock range of ring-oscillator-based frequency dividers. IEEE J Solid-State Circuits 43(3):656–671Google Scholar
  7. 7.
    Betancourt-Zamora R, Verma S, Lee T (2001) 1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers. Symposium on VLSI Circuits Digital Technical Papers, pp 47–50, 2001Google Scholar
  8. 8.
    Farazian M, Gudem P, Larson L (2009) A CMOS multi-phase injection-locked frequency divider for V-band operation. IEEE Micro Wirel Compon Lett 14(1):447–450Google Scholar
  9. 9.
    Hossain M, Carusone A (2009) CMOS oscillators for clock distribution and injection-locked deskew. IEEE J Solid-State Circuits 44(8):2138–2153Google Scholar
  10. 10.
    Ghilioni A, Decanis U, Monaco E, Mazzanti A, Svelto F (2011) A 6.5 mW inductorless CMOS frequency divider-by-4 operating up to 70 GHz. In: IEEE ISSCC digest of technical papers, pp 282–284, Feb 2011Google Scholar
  11. 11.
    Pellerano S, Mukhopadhyay R, Ravi A, Laskar J, and Palaskas Y (2008) A 39.1–41.6 GHz \(\Delta \Sigma \) fractional-N frequency synthesizer in 90 nm CMOS. In: IEEE ISSCC digest of technical papers, pp 484–630, Feb 2008Google Scholar
  12. 12.
    Scheir K, Vandersteen G, Rolain Y, Wambacq P (2009) A 57–66 GHz quadrature PLL in 45 nm digital CMOS. In: IEEE ISSCC digest of technical papers, pp 494–495, Feb 2009Google Scholar
  13. 13.
    Verma S, Rategh H, Lee T (2003) A unified model for injection-locked frequency dividers. IEEE J Solid-State Circuits 38(6):1015–1027Google Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Mohammed Farazian
    • 1
  • Prasad S Gudem
    • 1
  • Lawrence  E. Larson
    • 2
  1. 1.Qualcomm IncorporatedSan DiegoUSA
  2. 2.Brown School of Engineering Brown UniversityProvidenceUSA

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