Predictive Modeling of Carbon Nanotube Devices

Part of the Integrated Circuits and Systems book series (ICIR)


Silicon based devices have been the forerunner in mainstream computing for the last 40 years. Their success relies on simultaneously achieving sustainable scaling of physical dimensions and device performance [1]. However, such a scaling trend has been significantly slowing down in recent years due to fundamental physics, materials, and manufacturing limits. Examples of major bottlenecks for continual scaling include short channel effects, high leakage currents, large process variations and reliability issues [2–4]. These pitfalls are rendering design and fabrication of integrated circuits increasingly difficult with scaled silicon devices. As we approach these fundamental limits in planar CMOS process, it becomes imperative to search for alternative materials, structures, and devices to replace silicon transistor as the building block of future nanoelectronics.


Schottky Barrier Schottky Barrier Height Compact Model Quantum Capacitance Metallic Nanotubes 
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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.School of ECEEArizona State UniversityTempeUSA

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