Abstract
CMOS technology scaling is increasingly challenged by fundamental physics and manufacturing limits at the 22 nm node and beyond [1]. High-k/metal gate devices and strained silicon techniques help extend the lifetime of CMOS technology, but also complicate the fabrication process and increase the amount of variations. The situation is compounded by low power process, which has different device and design requirements from high performance process, and RC parasitics of scaled backend-of-the-line (BEOL) interconnect. During the pathway of scaling, process and design tradeoffs, such as those between power consumption and circuit performance, become much more complex, due to the issues in aggressively scaled CMOS technology and the implementation of new circuit design techniques. These challenges reduce the predictability of circuit performance and increase the development cycle for new products. In order to continue the design success with nanoscale CMOS, it requires an early comprehension of the technology impacts and adaptively making design decisions up front. Such a predictive capability helps identify potential issues, enables early design research, and guarantees the time to market. To accomplish this new design paradigm, it requires Predictive Technology Models (PTM) to assess performance trends, and to evaluate key modules before silicon is ready [2, 3].
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
The International Technology Roadmap for Semiconductors (ITRS), 2008.
W. Zhao and Y. Cao, “New generation of predictive technology modeling for sub-45 nm early design exploration,” IEEE Trans. Electron Devices, vol. 53, pp. 2816–2823, Nov. 2006.
W. Zhao, X. Li, M. Nowak, Y. Cao, “Predictive technology modeling for 32 nm low power design,” International Semiconductor Device Research Symposium, TA4-03, 2007.
D. Greenhill, “Design for reliability in CMOS VLSI,” Tutorial, International Solid-State Circuits Conference, 2002.
R. Heald, P. Wang, “Variability in sub-100 nm SRAM design,” ICCAD, pp. 347–352, 2004.
T. Sakurai, “Perspectives of low-power VLSI’s,” IEICE Trans. Electron, vol. E 87-C, no. 4, pp. 429–436, April 2004.
K. Roy, et al., “Gate leakage reduction for scaled devices using transistor stacking,” Trans. on VLSI, vol. 11, no. 4, pp. 716–730, August 2003.
S. Rodriguez and B. Jacob, “Energy/Power breakdown of pipelined nanometer caches (90 nm/65 nm/45 nm/32 nm),” ISLPED, pp. 25–30, 2006.
X. Li, W. Zhao, Y. Cao, Z. Zhu, J. Song, D. Bang, C.-C. Wang, S. H. Kang, J. Wang, M. Nowak, N. Yu, “Pathfinding for 22 nm CMOS designs using predictive technology models,” Custom Integrated Circuits Conference, pp. 227–230, 2009.
Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation,” Custom Integrated Circuits Conf., pp. 201–204, 2000.
W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. Nassif, K. J. Nowka and Y. Cao, “Rigorous extraction of process variations for 65-nm CMOS Design,” IEEE Trans. Semiconductor Manufacturing, vol. 22, pp. 196–203, Feb. 2009.
W. Zhao, X. Li, S. Gu, S. H. Kang, M. Nowak and Y. Cao, “Field-based capacitance modeling for sub-65 nm on-chip interconnect,” IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1862–1872, September 2009.
K.-L. Cheng, et al., “A Highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242μm2 SRAM Cell,” IEEE International Electron Devices Meeting, pp. 243–246, 2007.
S.-Y. Wu, et al., “A 32 nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM,” IEEE International Electron Devices Meeting, pp. 263–266, 2007.
C. H. Diaz, et al., “32 nm gate-first high-k/metal-gate technology for high performance low power applications,” IEEE International Electron Devices Meeting, pp. 629–632, 2008.
B. S. Haran, et al., “22 nm technology compatible fully functional 0.1 μm2 6 T-SRAM cell,” IEEE International Electron Devices Meeting, pp. 625–628, 2008.
S. Natarajan, et al., “A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291 Mb array,” IEEE International Electron Devices Meeting, pp. 941–943, 2008.
F. Arnaud, et al., “32 nm general purpose bulk CMOS technology for high performance applications at low voltage,” IEEE International Electron Devices Meeting, pp. 633–636, 2008.
X. Zhang, et al., “On zero clock skew hold time failure in scan test,” Solid-State and Integrated-Circuit Technology, pp. 2070-2074, 2008.
S. Nassif, N. Mehta, Y. Cao, “A resilience roadmap,” Design, Automation and Test in Europe, pp. 1011-1016, 2010.
K. Bernstein, et al., “High-performance CMOS variability in the 65-nm regime and beyond,” IBM J. Res. & Dev., vol. 50, no. 4/5, pp. 433–449, Jul./Sep., 2006.
W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Design Automation Conference, pp. 364–369, 2007.
R. Vattikonda, W. Wang, Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” Design Automation Conference, pp. 1047-1052, 2006.
K. Mistry, et al., “A 45 nm logic technology with high-k + metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” IEEE International Electron Devices Meeting, pp. 247–250, 2007.
Y. Ye, F. Liu, S. Nassif, Y. Cao, “Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,” Design Automation Conference, pp. 900–905, 2008.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Cao, Y. (2011). Design Benchmark with Predictive Technology Model. In: Predictive Technology Model for Robust Nanoelectronic Design. Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0445-3_7
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0445-3_7
Published:
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4614-0444-6
Online ISBN: 978-1-4614-0445-3
eBook Packages: EngineeringEngineering (R0)