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Clocks and Resets

  • Mohit Arora
Chapter

Abstract

The cost of designing ASICs is increasing every year. In addition to the non-recurring engineering (NRE) and mask costs, development costs are increasing due to ASIC design complexity. To overcome the risk of re-spins, high NRE costs, and to reduce time-to-market delays, it has become very important to design the first time working silicon.

Keywords

Data Path Clock Signal Flip Flop Combinational Logic Synthesis Tool 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

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    Mohit Arora, Prashant Bhargava, Amit Srivastava, Optimization and Design Tips for FPGA/ASIC(How to make the best designs), DCM Technologies, SNUG India, 2002Google Scholar
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    Application Note, ASIC design guidelines, Atmel Corporation, 1999Google Scholar
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    Cummings CE, Sunburst Design, Inc.; Mills D, LCDM Engineering (2002) Synchronous resets? Asynchronous resets? I am so confused! How will I ever know which to use? SNUG, San JoseGoogle Scholar
  4. 4.
    Application Note, Clock skew and short paths timing, Actel Corporation, 2004Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.Freescale SemiconductorFaridabadIndia

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