• Kunio Uchiyama
  • Fumio Arakawa
  • Hironori Kasahara
  • Tohru Nojiri
  • Hideyuki Noda
  • Yasuhiro Tawara
  • Akio Idehara
  • Kenichi Iwata
  • Hiroaki Shikano


Since the mid-1990s, the concept of “digital convergence” has been proposed and discussed from both technological and business viewpoints [1]. In the twenty-first century, “digital convergence” has become stronger and stronger in various digital fields. It is especially notable in the recent trend in digital consumer products such as cellular phones, car information systems, and digital TVs (Fig. 1.1) [2, 3]. This trend will become more widespread in various embedded systems, and it will expand the conventional market due to the development of new functional products and also lead to the creation of new markets for goods such as robots.


  1. 1.
    Negroponte N (1995) Being digital. Knopf, New YorkGoogle Scholar
  2. 2.
    Uchiyama K (2008) Power-efficient heterogeneous parallelism for digital convergence, digest of technical papers of 2008 Symposium of VLSI circuits, Honolulu, USA, pp 6–9Google Scholar
  3. 3.
    Uchiyama K (2010) Power-efficient heterogeneous multicore for digital convergence, Proceedings of 10th International Forum on Embedded MPSoC and Multicore, Gifu, Japan, pp 339–356Google Scholar
  4. 4.
    Liu T-M, Lin T-A, Wang S-Z, Lee W-P, Hou K-C, Yang J-Y, Lee C-Y (2006) A 125uW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Application, Digest of Technical Papers of 2006 IEEE International Solid-State Circuits Conference, San Francisco, USA, pp 402–403Google Scholar
  5. 5.
    Iwata K, Mochizuki S, Shibayama T, Izuhara F, Ueda H, Hosogi K, Nakata H, Ehama M, Kengaku T, Nakazawa T, Watanabe H (2008) A 256 mW Full-HD H.264 High-Profile CODEC Featuring Dual Macroblock-Pipeline Architecture in 65 nm CNOS, Digest of Technical Papers of 2008 Symposium of VLSI circuits, Honolulu, USA, pp 102–103Google Scholar
  6. 6.
    Hariyama M, Kazama H, Kameyama M (2000) VLSI Processor for Hierarchical Template Matching and Its Application to a Ball-Catching Robot System, IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), vol 2, pp 613–618Google Scholar
  7. 7.
    Kazama H, Hariyama M, Kameyama M (2000) Design of a VLSI processor based on an immediate output generation scheduling for ball-trajectory prediction. J Robot Mechatron 12(5):534–540Google Scholar
  8. 8.
    Kawasaki S (1994) SH-II: a low power RISC micro for consumer applications. Hot Chips VI:79–103Google Scholar
  9. 9.
    Narira S, Ishibashi K, Tachibana S, Norisue K, Shimazaki Y, Nishimoto J, Uchiyama K, Nakazawa T, Hirose K, Kudoh I, Izawa R, Matsui S, Yoshioka S, Yamamoto M, Kawasaki I (1995) A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing, 1995 Symposium on VLSI Circuits, Dig. Tech. Papers, pp 59–60Google Scholar
  10. 10.
    Hasegawa A, Kawasaki I, Yamada K, Yoshioka S, Kawasaki S, Biswas P (1995) SH3: high code density, low power. IEEE Micro 15(6):11–19CrossRefGoogle Scholar
  11. 11.
    Maejima H, Kainaga M, Uchiyama K (1997) Design and architecture for low-power/high-speed RISC microprocessor: SuperH. IEICE Trans Electron E80-C(12):1593–1545Google Scholar
  12. 12.
    Arakawa F, Nishii O, Uchiyama K, Nakagawa N (1997) SH4 RISC microprocessor for multimedia. HOT Chips IX:165–176Google Scholar
  13. 13.
    Uchiyama K (1998) Low-power, high-performance Microprocessors for Multimedia Applications, Cool Chips I, An International Symposium on Low-Power and High-Speed Chips, pp 83–98Google Scholar
  14. 14.
    Arakawa F, Nishii O, Uchiyama K, Nakagawa N (1998) SH4 RISC multimedia microprocessor. IEEE Micro 18(2):26–34CrossRefGoogle Scholar
  15. 15.
    Nishii O, Arakawa F, Ishibashi K, Nakano S, Shimura T, Suzuki K, Tchibana M, Totsuka Y, Tsunoda T, Uchiyama K, Yamada T, Hattori T, Maejima H, Nakagawa N, Narita S, Seki M, Shimazaki Y, Satomura R, Takasuga T, Hasegawa A (1998) A 200 MHz 1.2 W 1.4GFLOPS Microprocessor with Graphic Operation Unit, 1998 IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp 288–289Google Scholar
  16. 16.
    Mizuno H, Ishibashi K, Shimura T, Hattori T, Narita S, Shiozawa K, Ikeda S, Uchiyama K (1999) An 18-μA standby current 1.8 V 200-MHz microprocessor with self-substrate-biased data-retention mode. IEEE J Solid-State Circuits 34(11):1492–1500CrossRefGoogle Scholar
  17. 17.
    Kamei T, et al (2004) A resume-standby application processor for 3G cellular phones, ISSCC Dig Tech Papers:336–337, 531Google Scholar
  18. 18.
    Ishikawa M, et al (2004) A resume-standby application processor for 3G cellular phones with low power clock distribution and on-chip memory activation control, COOL Chips VII Proceedings, vol I, pp 329–351Google Scholar
  19. 19.
    Arakawa F, et al (2004) An embedded processor core for consumer appliances with 2.8GFLOPS and 36 M Polygons/s FPU. IEICE Trans Fundamentals, E87-A(12):3068–3074Google Scholar
  20. 20.
    Ishikawa M, et al (2005) A 4500 MIPS/W, 86 μA resume-standby, 11 μA ultra-standby application processor for 3G cellular phones. IEICE Trans Electron E88-C(4):528–535Google Scholar
  21. 21.
    Arakawa F, et al (2005) SH-X: An Embedded Processor Core for Consumer Appliances, ACM SIGARCH Computer Architecture News 33(3), pp 33–40Google Scholar
  22. 22.
    Yamada T, et al (2005) Low-Power Design of 90-nm SuperHTM Processor Core, Proceedings of 2005 IEEE International Conference on Computer Design (ICCD), pp 258–263Google Scholar
  23. 23.
    Arakawa F, et al (2005) SH-X2: An Embedded Processor Core with 5.6 GFLOPS and 73 M Polygons/s FPU, 7th Workshop on Media and Streaming Processors (MSP-7), pp 22–28Google Scholar
  24. 24.
    Yamada T et al (2006) Reducing Consuming Clock Power Optimization of a 90nm Embedded Processor Core. IEICE Trans Electron E89–C(3):287–294CrossRefGoogle Scholar
  25. 25.
    Kodama T, Tsunoda T, Takada M, Tanaka H, Akita Y, Sato M, Ito M (2006) Flexible Engine: A dynamic reconfigurable accelerator with high performance and low power consumption, in Proc. of the IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips IX)Google Scholar
  26. 26.
    Noda H et al (2007) The design and implementation of the massively parallel processor based on the matrix architecture. IEEE J Solid-State Circuits 42(1):183–192MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Kunio Uchiyama
    • 1
  • Fumio Arakawa
    • 2
  • Hironori Kasahara
    • 3
  • Tohru Nojiri
    • 4
  • Hideyuki Noda
    • 5
  • Yasuhiro Tawara
    • 2
  • Akio Idehara
    • 6
  • Kenichi Iwata
    • 7
  • Hiroaki Shikano
    • 4
  1. 1.Research and Development Group Hitachi, Ltd.Chiyoda-kuJapan
  2. 2.Renesas Electronics Corp.Kodaira-shiJapan
  3. 3.Green Computing SystemsWaseda University R&D CenterShinjuku-kuJapan
  4. 4.Central Research Lab. Hitachi, Ltd.Kokubunji-shiJapan
  5. 5.Renesas Electronics Corp.Itami-shiJapan
  6. 6.Nagoya Works, Mitsubishi Electric Corp.Higashi-kuJapan
  7. 7.Renesas Electronics Corp.KodairaJapan

Personalised recommendations