Abstract
The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
Notes
- 1.
The term is used herein in a more generic way than in [16].
- 2.
In practice, design patterns try to fulfill high level requirements that require a global strategy to be accomplished. The selection of the strategies is based on heuristics extracted from good design practices.
- 3.
AspectJ [17], a well-known AOP approach for Java, uses pointcut and advice as operators.
- 4.
They can refer to the entire application, a specific function, all or a specific loop, or even a specific location in the code for which an annotated label in the C code is used.
- 5.
E.g., the C-to-VHDL generator used in the back-end of CoSy may not support all C constructs.
- 6.
It includes annotations of customized bit-widths, statement latencies and scheduling, etc.
- 7.
During the design flow a join point might be removed by a previous tool’s action or might be different from the original when a previous tool transforms the code.
- 8.
LARA is currently being designed and the version presented here uses and extends some of the concepts proposed in [22].
- 9.
Strength reduction can also be applied to optimize the calculation of array indexing of z, i.e., 64*j used in z[i + 64*j] and in z[i + 1+64*j], lines 11 and 12 in Fig. 9. The expression 64*j can be translated to j < < 6 which can be implemented in hardware with the 26 least significant bits of j concatenated with six zeros.
References
K. Paulsson, M. Hübner, and J. Becker, “Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration,” in First NASA/ESA Conf. on Adaptive Hardware and Systems (AHS’2006), 15–18 June 2006, pp. 288–291.
G. Kiczales, “Aspect-Oriented Programming,” in ACM Computing Surveys (CSUR), special issue: position statements on strategic directions in computing research, 1996. 28(4es).
T. Elrad, R. Filman, A. Bader, “Aspect-Oriented Programming,” in Communications of the ACM, Vol. 44, Issue 10, Oct. 2001, pp. 29–32.
G. Kiczales, J. Lamping, A. Mendhekar, C. Maeda, C. Lopes, J.-M. Loingtier, and J. Irwin, “Aspect Oriented Programming,” in Proc. of the European Conference on Object-Oriented Programming (ECOOP’97), Finland. Springer-Verlag LNCS 1241. June 1997.
J. Irwin, J.-M. Loingtier, J. Gilbert, G. Kiczales, J. Lamping, A. Mendhekar, and T. Shpeisman, “Aspect-Oriented Programming of Sparse Matrix Code,” in Proc. Int’l Scientific Computing in Object-Oriented Parallel Environments (ISCOPE’97), Springer-Verlag, LNCS 1343, 1997, pp. 249–256.
S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, and E. Panainte, “The Molen Polymorphic Processor,” in IEEE Trans. on Computers, Nov. 2004, 53(11):1363–1375.
D. Boland, and G. Constantinides, “Automated Precision Analysis: A Polynomial Algebraic Approach” in Proc. IEEE Int’l Symp. on Field-Programmable Custom Computing Machines (FCCM’10), 2–4 May, 2010, pp. 157–164.
J. Clark, G. Constantinides, and P. Cheung, “Word-length selection for power minimization via nonlinear optimization,” in ACM Trans. Design Autom. Electron. Syst. (TODAES), 14(3), May 2009.
D. Lee, J. Villasenor, “A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation,” in IEEE Trans. on Computers, April, 2007, pp. 567–571.
W. Osborne, R. Cheung, J. Coutinho, W. Luk, and O. Mencer, “Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems,” in Proc. IEEE Int’l Conf. on Field Programmable Logic and Applications (FPL’07), 27–29 Aug. 2007, pp. 617–620.
A. DeHon, J. Adams, M. DeLorimier, N. Kapre, Y. Matsuda, H. Naeimi, M. Vanier, and M. Wrighton, “Design Patterns for Reconfigurable Computing,” in Proc. IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM’04), April 20–23, 2004, pp. 13–23.
Z. Li, and T. Bui, “Robot Path Planning Using Fluid Model,” in Journal of Intelligent and Robotic Systems, v. 21, 1998, pp. 29–50.
K. Valavanis, T. Hebert, R. Kolluru, and N. Tsourveloudis, “Mobile Robot Navigation in 2-D Dynamic Environments Using an Electrostatic Potential Field,” in IEEE Trans. Sys. and Cybernetics, 30(2), March 2000, pp. 187–196.
ISO/IEC 11172–3 “Information technology – Coding of moving pictures and associated audio for digital storage media at up to about 1.5 Mbit/s – Part 3: Audio”.
ISO/IEC 13818–3 “Information technology – Generic coding of moving pictures and associated audio information – Part 3: Audio”.
R. Lämmel, E. Visser, and J. Visser, “Strategic programming meets adaptive programming,” In Proc. 2nd Int’l Conf. on Aspect-Oriented Software Development (AOSD’03), Boston, Mass., March 17–21, 2003. ACM, New York, NY, USA, pp. 168–177.
J. Gradecki, and N. Lesiecki, Mastering AspectJ: Aspect-Oriented Programming in Java, Wiley, 2003.
W. Luk, J. Coutinho, T. Todman, Y. Lam, W. Osborne, K. Susanto, Q. Liu, and W. Wong, “A High-Level Compilation Toolchain for Heterogeneous Systems,” in Proc. IEEE Int’l SOC Conference (SOCC‘09), Sept. 2009, pp. 9–18.
ACE CoSy compiler development system, http://www.ace.nl/compiler/cosy.html.
ACE – Associated Compiler Experts bv., “CoSy CCMIR Definition”, Ref. CoSy-8002-ccmir, 2008.
Y. Yankova, K. Bertels, S. Vassiliadis, R. Meeuws, and A. Virginia, “Automated HDL Generation: Comparative Evaluation,” In Proc. Int’l Symp. on Circuits and Systems (ISCAS’07), May 2007, pp. 2750–2753.
J. Cardoso, P. Diniz, M. Monteiro, J. Fernandes, and J. Saraiva, “A Domain-Specific Aspect Language for Transforming MATLAB Programs,” in Domain-Specific Aspect Language Workshop (DSAL’2010), part of AOSD’2010, Rennes & Saint Malo, France, March 15–19, 2010.
J. Cardoso, and P. Diniz, Compilation Techniques for Reconfigurable Architectures, Springer, Oct. 2008.
J. Cardoso, P. Diniz, and M. Weinhardt, “Compiling for Reconfigurable Computing: A Survey,” in ACM Computing Surveys (CSUR), Vol. 42, No. 4, Article 13, June 2010, pp. 1–65.
P. Diniz, M. Hall, J. Park, B. So and H. Ziegler, “Automatic Mapping of C to FPGAs with the DEFACTO Compilation and Synthesis Systems,” in Elsevier Journal on Microprocessors and Microsystems, Vol. 29, Issues 2–3, 1 April 2005, pp. 51–62.
J. Cardoso, and H. Neto, “Compilation for FPGA-Based Reconfigurable Hardware,” in IEEE Design & Test of Computers Magazine, March/April, 2003, vol. 20, no.2, pp. 65–75.
M. Weinhardt, W. Luk, “Pipeline vectorization,” in IEEE Trans. on CAD of Integrated Circuits and Systems, 20(2), 2001, pp. 234–248.
Q. Liu, G. Constantinides, K. Masselos, and P. Cheung, “Combining Data Reuse with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework”, in IEEE Trans. on Computer-Aided Design, Vol. 28, Issue 3, March 2009, pp. 305–315
D. Lee, A. Abdul Gaffar, O. Mencer, and W. Luk, “Optimizing hardware function evaluation,” in IEEE Transactions on Computers, vol. 54, no. 12, Dec. 2005, pp. 1520–1531.
Y. Yankova, K. Bertels, S. Vassiliadis, R. Meeuws, and A. Virginia, “Automated HDL Generation: Comparative Evaluation,” In Proc. Int’l Symp. on Circuits and Systems (ISCAS2007), May 2007.
E. Panainte, K. Bertels, and S. Vassiliadis, “The Molen Compiler for Reconfigurable Processors,” in ACM Trans. in Embedded Computing Systems (TECS), 6(1), Article 6, Feb. 2007.
E. Panainte, K. Bertels, and S. Vassiliadis, “Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration,” in Journal of VLSI Signal Processing, 43(2), June 2006, pp. 161–172.
J. Cardoso, “On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures,” in IEEE Trans. on Computers, Vol. 52, No. 10, Oct. 2003, pp. 1362–1375.
Q. Liu, T. Todman, J. Coutinho, W. Luk, and G. Constantinides, “Optimising designs by combining model-based and pattern-based transformations”, in Proc. 19th Int’l Conf. on Field Programmable Logic and Applications (FPL’09), Aug. 31-Sept. 2, 2009, pp. 308–313.
J. Coutinho, J. Jiang, and W. Luk, “Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation,” in Proc. IEEE Symp. on Field Programmable Custom Computing Machines (FCCM’05), 18–20 April, 2005, pp. 245–254.
K. Bertels, V. Sima, Y. Yankova, G. Kuzmanov, W. Luk, J. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, A. Michelotti, “HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms,” in IEEE Micro, 30(5): 2010, pp. 88–97.
M. Bowen, Handel-C Language Ref. Manual, Embedded Solutions Ltd., 2.1 ed., 1998.
Mitrionics AB Inc., The Mitrion Processor, Product Overview, Sweden, 2005. http://www.mitrion.com (accessed on Dec. 2010).
Nallatech, http://www.nallatech.com (accessed on Dec. 2010).
J. Tripp, M. Gokhale, K. Peterson, “Trident: From High-Level Language to Hardware Circuitry,” in IEEE Computer, March 2007, vol. 40, no 3, pp. 28–37.
M. Gokhale, J. Stone, J. Arnold, and M. Kalinowski, “Stream-Oriented FPGA Computing in the Streams-C High Level Language,” in Proc. IEEE Symp. on FPGAs for Custom Computing Machines (FCCM’00), April 2000, pp. 126–135.
Z. Guo, W. Najjar, and A. Buyukkurt, “Efficient Hardware Code Generation for FPGAs,” in ACM Trans. on Architecture and Compiler Optimizations (TACO) Vol. 5, No. 1, Article 6, May 2008.
Impulse Accelerated Technologies, Inc., http://www.impulseaccelerated.com/ (Dec. 2010).
Catapult C Synthesis Overview, http://www.mentor.com/esl/catapult/ (Dec. 2010).
C. Huang, S. Ravi, A. Raghunathan, and N. Jha, “Synthesis of heterogeneous distributed architectures for memory-intensive applications,” in Proc. Int’l Conf. Computer-Aided Design (ICCAD’03), Nov. 2003, pp. 46–53.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
Cardoso, J.M.P. et al. (2011). REFLECT: Rendering FPGAs to Multi-core Embedded Computing. In: Cardoso, J., Hübner, M. (eds) Reconfigurable Computing. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0061-5_11
Download citation
DOI: https://doi.org/10.1007/978-1-4614-0061-5_11
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-0060-8
Online ISBN: 978-1-4614-0061-5
eBook Packages: EngineeringEngineering (R0)