Abstract
BEYOND-3G WIRELESS TELECOM SYSTEMS WILL REQUIRE low-power multi-standard chipsets that are capable to operate over a number of different co-existing communication protocols, signal conditions, battery status, etc. [Bran05]. An efficient implementation of these chipsets demands for reconfigurable transceiver blocks that can adjust their circuit parameters to the diverse specifications with adaptive power consumption and at the lowest cost. One of the most challenging building blocks in multi-standard receivers is the ADC, because of the assorted signal bandwidths and dynamic ranges that can be required to properly handle the A/D conversion for several operation modes [Gula01]. Compared to other data conversion techniques, SD modulators are very suited for the implementation of multi-standard, multi-mode ADCs in highly integrated transceivers using low-cost digitally-oriented nanometer CMOS technologies. On the one hand, the key principles of SD modulators (oversampling and noise shaping) make them robust with respect to circuit errors. On the other, since both principles determine the dynamic range of the SD modulator, their variations can easily contribute to adapt the converter performance to different specifications with large hardware reuse [Burg01][Mill03][Veld03][Chri07][Crom09].
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Notes
- 1.
Sometimes a reconfigurable LNA is employed when the standards share the same RF band [Bran05].
- 2.
Initial estimations of the power consumption showed that the power of the main building blocks in this modulator were dominated by this operation mode to such an extent that the obtained performance was really degraded. Moreover, this operation mode also dominates the power of the remaining ones because the building blocks were not flexible enough to work with such a large difference in the biasing and, consequently, in the power as well. The demanding speed requirements of this standard need a more efficient SDM architecture, as those presented in Chaps. 5 and 6.
- 3.
The use of a multi-bit quantizer—and DAC—for only the last stage, allows a dual-quantization scheme in which the quantization noise of the overall modulator decreases while the non-linearities of the multi-bit DAC are filtered by an order equal to the number of integrators in all the precedent stages.
- 4.
Note that dBFS is defined as dB relative to the FS, where the FS is given by the quantizer reference voltage.
- 5.
If multi-bit quantization is used in the modulator last stage, its integrator coefficients are usually doubled in order to operate with an unity-gain multi-bit quantizer and make its implementation easier. This, together with the larger integrator load due to the multi-bit quantizer, normally prevents from using the same electrical design.
- 6.
Note that the gain of the PGA in Fig. 4.1 needs to be adjusted, thus, to provide this input level.
- 7.
Note that the sizing of the amplifiers is not modified with the operation mode. This would have entailed a more complex transistor-level design.
- 8.
Note that the most important contribution to the overall modulator thermal noise comes from the first integrator since thermal noise of the remaining integrators suffers a filtering whose order depends on the location of the corresponding integrator in the modulator.
- 9.
Due to the layout separation into different regions in order to reduce switching noise coupling, the clock phases generator —located in the digital region— is placed far away from the switches where the clock phases must be routed.
- 10.
In this case, the same functionality can be obtained removing the last level of inverters in the tree and taking the phase from the previous level. However, the critical path would change.
- 11.
Only MiM capacitors and wide routing lines with stacked metal layers are visible after passivation.
- 12.
In this case, a voltage adaptation of the 3.3-V supply to the 1.2-V reference will be needed.
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Morgado, A., del Río, R., de la Rosa, J.M. (2011). A 130-nm CMOS Reconfigurable 2-1-1 Cascade SC ΣΔM for GSM/BT/UMTS. In: Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-0037-0_4
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DOI: https://doi.org/10.1007/978-1-4614-0037-0_4
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