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Abstract

Routing of VLSI chips is a complex and time consuming task. To manage the complexity of the problem, routing is attempted at different levels. At the highest level the areas set aside for routing nets between different functional blocks on the chip surface is divided into rectangular routing areas called channels. This step also decides on the order in which channels should be routed. The second step involves deciding the channels that each net passes through. The final step of routing is the detailed routing of each channel which is discussed in this chapter.

Keywords

Greedy Algorithm Human Designer VLSI Chip Interconnection Layer Interconnection Wire 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1986

Authors and Affiliations

  • Rostam Joobbani
    • 1
  1. 1.Carnegie-Mellon UniversityUSA

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