Drain-Induced Barrier Lowering In Short Channel Transistors

  • Kit Man Cham
  • Soo-Young Oh
  • Daeje Chin
  • John L. Moll
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 7)


Drain-induced barrier lowering (DIBL)[7.1]-[7.6] has been studied by many workers.


Current Path Potential Profile Gate Bias Short Channel Potential Barrier Height 
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  1. [7.1]
    R. R. Troutman, “VLSI Limitations from Drain-Induced Barrier Lowering,”IEEE Trans. Electron Devices,ED-27, April 1979, pp. 461–468.Google Scholar
  2. [7.2]
    R. R. Troutman, “Subthreshold Design Considerations for Insulated Field Effect Transistors,”IEEE J. Solid State Circuits,SC-9, April 1974, pp. 55–60.Google Scholar
  3. [7.3]
    B. Eitan and D. Frohman-Bentchkowsky, “Surface Conduction in Short Channel MOS Devices as a Limitation to VLSI Scaling,”IEEE Trans. Electron Devices,ED-26, April 1979, pp. 254–266Google Scholar
  4. [7.4]
    H. Masuda, M. Nakai, and M. Kubo, “Characteristics and Limitation of Scaled-Down MOSFET’s Due to Two-Dimensional Field Effect,”IEEE Trans. Electron Devices,ED-26, June 1979, pp. 980–986.Google Scholar
  5. [7.5]
    K. M. Cham and S. Y. Chiang, “Device Design for the Submicrometer P-Channel FET with n+ Polysilicon Gate,”IEEE Trans. Electron Devices,ED-31, July 1984, pp. 964–968.Google Scholar
  6. [7.6]
    J. J. Barnes, K. Shimohigashi, and R. Dutton, “Short-Channel MOSFET’s in the Punchthrough Current Mode,”IEEE Trans. Electron Devices,ED-26, April 1979, pp. 446–453Google Scholar
  7. [7.7]
    Y. A. El-Mansy and R. A. Burghard, “Design Parameters of the Hi-C DRAM Cell,”IEEE J. Solid-State Circuits,SC-17, Oct 1982, pp. 951–956.Google Scholar

Copyright information

© Springer Science+Business Media New York 1986

Authors and Affiliations

  • Kit Man Cham
    • 1
  • Soo-Young Oh
    • 1
  • Daeje Chin
    • 2
  • John L. Moll
    • 1
  1. 1.Hewlett-Packard LaboratoriesUSA
  2. 2.IBM—Thomas J. Watson Research CenterUSA

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