Simulation Tools for VLSI

  • Christopher J. Terman
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 24)

Abstract

Simulation plays an important role in the design of integrated circuits. Using simulation, a designer can determine both the functionality and the performance of a design before the expensive and time-consuming step of manufacture. The ability to discover errors early in the design cycle is especially important for MOS circuits, where recent advances in manufacturing technology permit the designer to build a single circuit that is considerably larger than ever before possible. This paper reviews the simulation techniques which are commonly used for the simulation of large digital MOS circuits.

Keywords

Expense Lution Tate 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

Circuit-level simulators

  1. B. AckLand and N. Weste, “Functional Verification in an Interactive IC Design Environment,” Proceedings of the Second Caltech Conference on Very Large Scale Integration, January 1981.Google Scholar
  2. V. Agrawal, et al, “A Mixed-mode Simulator,” Proceedings of 17th Design Automation Conference, June 1980.Google Scholar
  3. B. Chawla, H. Gummel, and P. Kozak, “MOTIS-An MOS Timing Simulator”, IEEE Transactions on Circuits and Systems, Vol. CAS-22, No. 13, December 1975.Google Scholar
  4. S. Fan, M. Y. Hseuh, A. Newton, and D. Pederson, “MOTIS-C: A New Circuit Simulator for MOS LSI Circuits,” Proceedings IEEE International Symposium on Circuits and Systems, April 1977.Google Scholar
  5. G. D. Hachtel, et al, “The Sparse Tableau Approach to Network Analysis and Design,” IEEE Transactions on Circuit Theory Vol. CT-18, January 1971.Google Scholar
  6. E. Lelarasmee, A. Ruehli, and A. Sangiovanni-Vincentelli, The Waveform Relaxation Method for Time Domain Analysis of Large Scale Integrated Circuits, Memorandum No. UCB/ERL M81/75, Electronics Research Laboratory, University of California, Berkeley, June 1981.Google Scholar
  7. L. Nagekl, SPICE2: A Computer Program to Simulate Semiconductor Circuits, ERL Memo No. ERL-M520, University of California, Berkeley, May 1975.Google Scholar
  8. H. Nham and A. Bose, “A Multiple Delay Simulator for MOS LSI Circuits”, Proceedings of 17th Design Automation Conference, June 1980.Google Scholar
  9. A. Newton, “Timing, Logic and Mixed-mode Simulation for Large MOS Integrated Circuits”, Computer Design Aids for VLSI Circuits, P. Antognetti, D.O. Pederson, H. De Man eds., Sijthoff & Noordhoff, Rockville, Maryland, 1981.Google Scholar
  10. A. Newton and A. Sangiovanni-Vincentelli, Relaxation-based Electrical Simulation, University of California, Berkeley, 1983.Google Scholar
  11. K. Okasaki, T. Moriya, and T. Yahara, “A Multiple Media Delay Simulator for MOS LSI Circuits,” Proceedings of 20th Design Automation Conference, June 1983.Google Scholar
  12. A. Sangiovanni-Vincentelli, “Circuit Simulation”, Computer Design Aids for VLSI Circuits, P. Antognetti, D.O. Pederson, H. De Man eds., Sijthoff & Noordhoff, Rockville, Maryland, 1981.Google Scholar
  13. J. Vlach and K. Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold, New York, New York, 1983.Google Scholar
  14. W. Weeks, et al, “Algorithms for ASTAP-A Network Analysis Program,” IEEE Transactions on Circuit Theory, Vol. CT-20, November 1973.Google Scholar

Switch-level simulators and hybrid models

  1. R. Bryant, Logic Simulation of MOS LSI, M.I.T. Laboratory for Computer Science TR-259, 1981.Google Scholar
  2. P. Flake, P. Moorby, and G. Musgrave, “An Algebra for Logic Strength Manipulation,” Proceedings of 20th Design Automation Conference, June 1983.Google Scholar
  3. M. Horowitz, “Timing Models for MOS Pass Networks,” Proceedings of the IEEE International Symposium on Circuits and Systems, 1983.Google Scholar
  4. N. Jouppi, “TV: An nMOS Timing Analyzer,” Proceedings of the Third Caltech VLSI Conference, 1983.Google Scholar
  5. J. Ousterhout, “Crystal: A Timing Analyzer for nMOS VLSI Circuits,” Proceedings of the Third Caltech VLSI Conference, 1983.Google Scholar
  6. P. Penfield and J. Rubinstein, Signal Delay in RC Tree Networks, M.I.T. VLSI Memo No. 81–40, January 1981.Google Scholar
  7. D. Pilling and H. Sun, “Computer-Aided Prediction of Delays in LSI Logic Systems,” Proceedings of 10th Design Automation Workshop, June 1973.Google Scholar
  8. C. Terman, “Timing Simulation for Large Digital MOS Circuits,” Advances in Computer-Aided Engineering Design, Volume 1, JAI Press Inc., 1985.Google Scholar

Gate-level simulators

  1. Z. Barzilai, et al, “Simulating Pass Transistor Circuits using Logic Simulation Machines,” Proceedings of 20th Design Automation Conference, June 1933.Google Scholar
  2. G. Case, “SALOGS-IV-A Program to Perform Logic Simulation and Fault Diagnosis,” Proceedings of 15th Design Automation Conference, June 1978.Google Scholar
  3. M. Denneau, “The Yorktown Simulation Engine,” Proceedings of 19th Design Automation Conference, June 1982.Google Scholar
  4. P. Flake, P. Moorby, and G. Musgrave, “Logic Simulation of Bi-directional Tri-state Gates,” Proceedings of IEEE International Conference on Circuits and Computers, October 1980.Google Scholar
  5. D. Holt and D. Hutchings, “A MOS/LSI Oriented Logic Simulator,” Proceedings of 18th Design Automation Conference, June 1981.Google Scholar
  6. R. McDermott, “Transmission Gate Modeling in an Existing Three-value Simulator,” Proceedings of 19th Design Automation Conference, June 1982.Google Scholar
  7. G. Pfister, “The Yorktown Simulation Engine: Introduction,” Proceedings of 19th Design Automation Conference, June 1982.Google Scholar
  8. W. Sherwood, “A MOS Modelling Technique for 4-State True-Value Hierarchical Logic Simulation,” Proceedings of 18th Design Automation Conference, June 1981.Google Scholar
  9. S. Szygenda, “TEGAS2-Anatomy of a General Purpose Test Generation and Simulation System for Digital Logic,” Proceedings of 9th ACM Design Automation Workshop, June 1972.Google Scholar
  10. S. Szygenda and E. Thompson, “Digital Logic Simulation in a Time-Based, Table- Driven Environment,” IEEE Computer, Vol. 8, March 1975.Google Scholar
  11. E. Thompson, et al, “Timing Analysis for Digital Fault Simulation Using Assignable Delays,” Proceedings of 11th Design Automation Conference, June 1974.Google Scholar
  12. E. Ulrich and T. Baker, “The Concurrent Simulation of Nearly Identical Digital Networks,” Proceedings of 10th Design Automation Workshop, June 1973.Google Scholar
  13. E. Ulrich, “Non-integral Event Timing for Digital Logic Simulation,” Proceedings of 13th Design Automation Conference, June 1976.Google Scholar
  14. LE-1000 Series Logic Evaluator Intermediate Form Specification, Release 1.0, Zycad Corporation, Roseville, MN, 1983.Google Scholar

Copyright information

© Kluwer Academic Publishers 1987

Authors and Affiliations

  • Christopher J. Terman
    • 1
  1. 1.Symbolics, Inc.CambridgeUSA

Personalised recommendations