Abstract
A method for comparing the asymptotic performance of different sorting algorithms for VLSI is proposed. For each algorithm it takes into account the maximal problem size that is realizable on a single chip under the restrictions imposed by the available technology. This sorting chip is used to perform a sort-split operation on blocks of data in an external merge algorithm for sorting arbitrarily large sets of data. The performance of the merge algorithm is determined by the execution time and period of the sorting chip used. Thus a realistic comparison of the practical feasability of sorting algorithms for VLSI is obtained.
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© 1987 Plenum Press, New York
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Lang, HW., Schimmler, M., Schmeck, H., Schröder, H. (1987). A Method for Realistic Comparisons of Sorting Algorithms for VLSI. In: Ghosh, S.P., Kambayashi, Y., Tanaka, K. (eds) Foundations of Data Organization. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1881-1_25
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DOI: https://doi.org/10.1007/978-1-4613-1881-1_25
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-9048-3
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