Placement and Global Routing of Standard Cell Integrated Circuits
This chapter presents the algorithms and the implementation of a standard cell placement and global routing package. This package, named TimberWolfSC,1 makes extensive use of the simulated annealing algorithm presented in the previous chapter. The generalized standard cell layout style handled by TimberWolfSC is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. An example of such a standard cell layout is shown in Figure 3.1.
KeywordsPenalty Function Simulated Annealing Algorithm Standard Cell Chip Area Macro Block
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