Abstract
This chapter presents the algorithms and the implementation of a standard cell placement and global routing package. This package, named TimberWolfSC,1 makes extensive use of the simulated annealing algorithm presented in the previous chapter. The generalized standard cell layout style handled by TimberWolfSC is characterized by horizontal rows of standard cells with pads placed around the periphery of the chip. Furthermore, macro blocks may be present on the chip. An example of such a standard cell layout is shown in Figure 3.1.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
All references to TimberWolfSC in this chapter and in this book refer to version 3.2. Work on TimberWolfSC has continued; for example, see: C. Sechen and K. W. Lee, “An Improved Simulated Annealing Algorithm for Row-Based Placement,” (1987).
S. Kirkpatrick, C. Gelatt, and M. Vecchi, “Optimization by Simulated Annealing,” (1983).
C. Sechen and A. Sangiovaimi-Vincentelli, “The TimberWolf Placement and Routing Package,” (1984).
C. Sechen and A. Sangiovaimi-Vincentelli, “The TimberWolf Placement and Routing Package,” (1985).
D. Mitra, F. Romeo, and A. Sangiovanni-Vincentelli, “Convergence and Finite-Time Behavior of Simulated Annealing,” (1985).
J. Kruskal, “On the Shortest Spanning Subtree of a Graph and the Traveling Salesman Problem,” (1956).
C. Horng and M. Lie, “An Automatic/Interactive Layout Planning System for Arbitrarily-Sized Rectangular Building Blocks,” (1981).
M. Lie and C. Horng, “A Bus Router for IC Layout,” (1982).
J. Krauskopf, Private Communication, (1986).
M. Roberts, Private Communication, (1986).
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1988 Kluwer Academic Publishers, Boston
About this chapter
Cite this chapter
Sechen, C. (1988). Placement and Global Routing of Standard Cell Integrated Circuits. In: VLSI Placement and Global Routing Using Simulated Annealing. The Kluwer International Series in Engineering and Computer Science, vol 54. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1697-8_3
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1697-8_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8957-9
Online ISBN: 978-1-4613-1697-8
eBook Packages: Springer Book Archive