In this chapter, we consider the problem of minimizing layout area of logic arrays. Most of the previous research efforts [DeSa83, HaNS82, WoLL87] on the subject have been concentrated on reducing layout area of Programmable Logic Arrays (PLA), a class of widely used logic arrays which are two-level implementations of logic functions. In general, multi-level implementations such as Gate Matrix, Weinberger Array, SLA, etc., can substantially reduce the total layout area and improve the speed performance of a circuit. Existing minimization methods that were primarily designed for PLA’s are no longer effective for these more general logic arrays. A general formulation of an array optimization problem for efficient layout of multi-level logic circuits was first proposed in [DeNe86] and further studied in [WoLi87b]. The general optimization problem includes compaction of Gate Matrix layouts, SLA’s, Weinberger Arrays, and for multiple folding of PLA’s as special cases. We shall present in this chapter an algorithm proposed in [WoLi87b] for the array optimization problem. As in [DeNe86], the approach of [WoLi87] is also based on the method of simulated annealing.
KeywordsSimulated Annealing Solution Space VLSI Design Adjacent Column Vertical Interval
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