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The Standard Logic Package

  • David R. Coelho

Abstract

The Standard Logic Package contains a collection of useful modelling facilities encapsulated in a VHDL package. This chapter will discuss this package in detail, highlighting the rationale behind each feature of the package and ways in which the package can be used to aid in modelling.

Keywords

Lookup Table True Logic Boolean Operator Type Definition Standard Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1989

Authors and Affiliations

  • David R. Coelho
    • 1
  1. 1.Vantage Analysis Systems, Inc.USA

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