Wafer-Level Integrated Systems pp 207-243 | Cite as

# General Testing Techniques

Chapter

## Abstract

In this chapter, techniques to generate test stimuli, apply those test to circuit functions and to evaluate the test results [1,2,3,4] are reviewed. The emphasis is on general purpose schemes, such as scan path design of VLSI circuits and syndrome test compression. Special purpose testing schemes (e.g. [5,6,7,8]) developed for specific system functions (PLA’s, random access memories, linear matrix operations, etc) are considered separately in the next chapter.

## Keywords

Test Vector Fault Coverage Linear Feedback Shift Register Clock Pulse Sequential Circuit
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© Kluwer Academic Publishers 1989