Abstract
The Restructurable VLSI project at MIT Lincoln Laboratory has developed a design methodology, new technology, and CAD tools for WSI. Six wafer scale systems have been fabricated and three of much larger size are being designed. Figure 1 shows one of these packaged WS circuits. The accomplishments and current research status of this project, which was conceived in 1979 [1], are described in this chapter.
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References
J. I. Raffel, “On the Use of Nonvolatile Programmable Links for Restructurable VLSI,” Proceedings of the 1979 Cal tech Conference on VLSI, Pasadena, CA, pp. 95–104.
J. I. Raffel, “The RVLSI Approach to Wafer Scale Integration,” in Wafer Scale Integration, ed. by C. Jesshope and W. Moore, Bristol: Adam Hilger, pp. 199–203, 1986.
J. A. Yasaitis, G. H. Chapman, and J. I. Raffel, “Low Resistance Laser Formed Lateral Links,” Electron Device Letters, vol. EDL-3, pp. 184–186, 1984.
J. I. Raffel, J. F. Freidin, and G. H. Chapman, “Laser Formed Connections Using Polyimide,” Applied Physics Letters, vol. 42, pp. 705–706, 1983.
G. H. Chapman, “Laser-Linking Technology For RVLSI,” in Wafer Scale Integration, ed by C. Jesshope and W. Moore, Bristol: Adam Hilger, pp. 204–215, 1986.
J. I. Raffel, M. L. Naiman, R. L. Burke, G. H. Chapman, and P. G. Gottschalk, “Laser Programmed Vias for Restructurable VLSI,” International Electron Devices Meeting Technical Digest, Washington, DC, pp. 132–135, 1980.
G. H. Chapman, J. I. Raffel, J. A. Yasaitis, and S. M. Cheston, “Laser Linking for Restructurable VLSI,” Conference on Lasers and Electro-optics Technical Digest, Phoenix, AZ, pp. 60–63, 1982.
B. Mathur, J. A. Burns, and G. H. Chapman, “Improvement of the AC Characteristics of an Amorphous Silicon-RVLSI Link Insulator by Hydrogenation,” presentation at Electronic Materials Conference, 1984.
G. H. Chapman, and J. A. Burns, “Enhanced Operation of Wafer-Scale Circuits Using Nitrided a-Si Laser Links,” Conference on Lasers and Electro-optics Technical Digest, San Francisco, CA, pp. 147–149, 1986.
J. A. Burns, G. H. Chapman, and B. L. Emerson, “Programmable Connections Through Plasma Deposited Silicon Nitride,” Electro-Chemical Society, vol. 86–2, pp. 481–482, 1986.
J. A. Bums, G. H. Chapman, and T. O. Herndon, “Applications of Plasma-Deposited SiN to Wafer-Scale Integrated Circuits,” IEEE Transactions on Electron Devices, vol. ED-34, pp. 2374–2375, 1987.
G. H. Chapman, and J. A. Burns, “Silicon Nitride as a Protection Layer for Laser Linked Wafer Scale Integration,” Conference on Lasers and Electro-optics Technical Digest, Baltimore, MD, pp. 270–271, 1987.
J. M. Canter, G. H. Chapman, B. Mathur, M. L. Naiman, and J. I. Raffel, “A Laser-Induced Ohmic Link for Wafer Scale Integration in Standard CMOS Processing,” IEEE Transactions on Electron Devices, vol. ED-33, p. 1861, 1986.
G. H. Chapman and J. I. Raffel, “Laser Linking for Defect Avoidance and Customisation,” Proceedings of the IFIP International Workshop on Wafer-Scale Integration, Brunel University, England, September 23–25, 1987, to be published.
J. M. Canter, G. H. Chapman, and J. I. Raffel, “A Laser-Diffused Link for Wafer-Scale Integration Using Standard CMOS Processing,” Conference on Lasers and Electro-optics Technical Digest, Anaheim, CA pp. 338–340, 1988.
S. S. Cohen and G. H. Chapman, “Laser Beam Processing and Wafer-Scale Integration,” Chapter in Beam Processing Technologies, ed. by N. G. Einspruch, S. S. Cohen, and R. N. Singh, Academic Press, to be published.
S. S. Cohen, P. W. Wyatt, G. H. Chapman, and J. M. Canter, “Laser-Induced Diode Linking for Wafer-Scale Integration,” IEEE Transactions on Electron Devices, vol. ED-35, pp. 1533–1550, 1988.
A. H. Anderson, “Computer Aided Design and Testing for RVLSI,” in Wafer Scale Integration, ed. by C. Jesshope and W. Moore., Bristol: Adam Hilger, pp. 216–222, 1986.
S. L. Garverick and E. A. Pierce, “A Single Wafer 16-Point 16 MHz FFT Processor,” Proceedings of the Custom Integrated Circuits Conference, pp. 244–248, 1983.
Stephen Slade, The T Programming Language, Englewood Cliffs: Prentice-Hall, Inc., 1987.
J. K. Ousterhout, G. T. Hamachi, R. R. Mayo, W. S. Scott, and G. S. Taylor, “Magic: A VLSI Layout System,” Proceedings of the 21st Design Automation Conference, Albuquerque, NM, pp. 152–159, 1984.
F. M. Rhodes, “Performance Characteristics of the RVLSI Technology,” in Wafer Scale Integration, ed by G. Saucier and J. Trilhe, New York: Elsevier Science Publishers, pp. 31–42, 1986.
P. W. Wyatt, J. I. Raffel, G. H. Chapman, B. Mathur, J. A. Burns, and T. O. Herndon, “Process Considerations in Restructurable VLSI for Wafer-Scale Integration,” Proceedings of International Electron Devices Meeting, San Francisco, CA, pp. 626–629, 1984.
F. M. Rhodes, “Applications of RVLSI to Signal Processing,” in Wafer Scale Integration, ed by C. Jesshope and W. Moore, Bristol: Adam Hilger, pp. 223–235, 1986.
J. I. Raffel, A. H. Anderson, G. H. Chapman, K. H. Konkle, B. Mathur, A. M. Soares, and P. W. Wyatt, “A Wafer-Scale Digital Integrator,” Proceedings of the IEEE International Conference on Computer Design, Port Chester, NY, pp. 121–126, 1984.
G. H. Chapman, A. H. Anderson, K. H. Konkle, B. Mathur, J. I. Raffel, and A. M. Soares, “Interconnection and Testing of a Wafer-scale Circuit via Laser Processing,” Conference on Lasers and Electro-Optics Technical Digest, Anaheim, CA, pp. 222–223, 1984.
J. I. Raffel, A. H. Anderson, G. H. Chapman, K. H. Konkle, B. Mathur, A. M. Soares, and P. W. Wyatt, “A Wafer-Scale Digital Integrator Using Restructurable VLSI,” IEEE Transactions on Electron Devices, vol. ED-32, pp. 479–486, 1985.
R. O. Duda and P. E. Hart, “Use of the Hough Transform to Detect Lines and Curves in Pictures,” Communications of the Association for Computing Machinery, vol. 15, pp. 11–15, 1972.
F. M. Rhodes, J. J. Dituri, G. H. Chapman, B. E. Emerson, A. M. Soares, and J. I. Raffel, “A Monolithic Hough Transform Processor Based on Restructurable VLSI,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 10, pp. 106–110, 1988.
J. R. Mann and F. M. Rhodes, “A Wafer Scale DTW Multiprocessor,” Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, Tokyo, Japan, pp. 1557–1560, April, 1986.
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Raffel, J., Anderson, A.H., Chapman, G.H. (1989). Laser Restructurable Technology and Design. In: Swartzlander, E.E. (eds) Wafer Scale Integration. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1621-3_7
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DOI: https://doi.org/10.1007/978-1-4613-1621-3_7
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