## Abstract

Research in the area of wafer scale integration has been conducted with varying degrees of success since the 1960s. Unfortunately, failures in this area have been much better publicized than successes. The especially spectacular failure of Trilogy [1] is still very well remembered though much less understood. Consequently, despite the undisputable potential of WSI, large area VLSI systems are still considered to be economically justifiable for military applications and technologically feasible only if fabricated in expensive research labs. Such opinions are supported both by a few publications and by the commonly held opinion that it is very hard to achieve a working VLSI circuit with an area much larger than 1 cm^{2} to 2 cm^{2}.

### Keywords

Assure Beach Polysilicon Mellon## Preview

Unable to display preview. Download preview PDF.

### References

- [1]D. L. Peltzer, “Wafer-Scale Integration; The Limits of VLSI?,” VLSI Design, pp. 43–47, September, 1983.Google Scholar
- [2]J. I. Raffel, A. H Anderson, G. H Chapman, K. H. Konkle, B. Mathur, A. M. Soares, and P. W. Wyatt, “A Wafer-Scale Digital Integrator Using Restructurable VLSI,” IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 399–409, 1985.CrossRefGoogle Scholar
- [3]J. I. Raffel, “On the Use of Nonvolatile Programmable Links for Restructurable VLSI,” Proceedings of the Caltech Conference on VLSI, pp. 95–104, 1979.Google Scholar
- [4]E. E. Swartzlander, Jr., “Technology and Architecture for Wafer Scale Integration,” IEEE CANDE Workshop, Santa Rosa, CA, 1988.Google Scholar
- [5]J. F. McDonald, B. J. Donlan, R. H. Steinvorth, and G. F. Taylor, “The Trials of Wafer Scale Integration,” IEEE Spectrum, pp. 32–39, October, 1984.Google Scholar
- [6]Y. Kitano, et al., “A 4 Mb Full-Wafer ROM,” IEEE International Solid-State Circuits Conference Digest, pp. 150–151, 1980.Google Scholar
- [7]C. L. Cohen, “Full-Wafer Memory for Color Displays has 1.5 Mb Capacity,” Electronics, pp. 77–78, January 26, 1984.Google Scholar
- [8]L. Bentley and C. R. Jesshope, “The Implementation of a Two-Dimensional Redundancy Scheme in a Wafer Scale High-Speed Disk Memory,” in Wafer Scale Integration, ed. by C. R. Jesshope and W. R. Moore, Bristol: Adam Hilger, pp. 187–197, 1986.Google Scholar
- [9]B. J. Donlan, G. F. Taylor, R. H. Steinvorth, A. S. Bergendahl, and J. F. McDonald, “Wafer Scale Integration Using Discretionary Microtransmission Line Interconnections,” in Wafer Scale Integration, ed. by C. R. Jesshope and W. R. Moore, Bristol: Adam Hilger, pp. 31–45, 1986.Google Scholar
- [10]J. Trilhe and G. Saucier, “WSI-Challenge of the Future,” Proceedings of VLSI and Computers, Hamburg, pp. 531–542, May 11–15, 1987.Google Scholar
- [11]W. Maly , M. E. Thomas, J. D. Chin, and D. M. Campbell, “Characterization of Type, Size and Density of Spot Defects in the Metalization Layer,” in Yield Modelling and Fault Tolerance in VLSI, ed. by W. Moore, W. Maly, and A. J. Strojwas, Bristol: Adam Hilger, 1988.Google Scholar
- [12]B. T. Murphy, “Cost Size Optima of Monolithic Integrated Circuits,” Proceedings of the IEEE, vol. 52, pp. 1537–1545, 1964.CrossRefGoogle Scholar
- [13]R. Seeds, “Yield and Cost Analysis of Bipolar LSI,” IEEE International Electron Devices Meeting Proceedings, 1967.Google Scholar
- [14]T. Okabe , M. Nagata, and S. Sumida, “Analysis of Integrated Circuits and a New Expression for the Yield,” Electrical Engineering in Japan, vol. 92, pp. 135–141, 1972.CrossRefGoogle Scholar
- [15]A. Gupta and J. W. Lathrop, “Yield Analysis of Large Integrated Circuit Chips,” IEEE Journal of Solid-State Circuits, vol. SC-7, pp. 389–395, 1972.CrossRefGoogle Scholar
- [16]R. M. Warner, “Applying a Composite Model to the IC Yield Problem,” IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 86–95, 1974.CrossRefGoogle Scholar
- [17]C. Stapper, “On a Composite Model to the IC Yield Problem,” IEEE Journal of Solid-State Circuits, vol. SC-10, pp. 537–539, 1975.CrossRefGoogle Scholar
- [18]W. Maly and J. Deszczka, “Yield Estimation Model for VLSI Artwork Evaluation,” Electronics Letters, vol. 19, pp. 226–227, 1983.CrossRefGoogle Scholar
- [19]C. H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,” IBM Journal of Research and Development, vol. 27, pp. 549–557, 1983.CrossRefGoogle Scholar
- [20]W. Maly, “Modelling of Point Defect Related Yield Losses for CAD of VLSI Circuits,” Proceedings of the International Conference on Computer Aided Design, pp. 161–163, 1984.Google Scholar
- [21]A.V. Ferris-Prabhu, “Defect Size Variations and Their Effect on the Critical Area of VLSI Devices,” IEEE Journal of Solid-State Circuits, vol. SC-20, pp. 874–878, 1985.CrossRefGoogle Scholar
- [22]J. Doi, W. Maly, and M. E. Thomas, “Detection and Physical Characterization of Spot Defects in Metal IC Interconnections,” Proceedings of the 172nd Electrochemical Society Meeting, p. 837, Honolulu, HI, 1987.Google Scholar
- [23]W. Maly, “Built-in Current Testing: Part I,” SRC-CMU Research Center for Computer Aided Design, Carnegie Mellon University, Research Report No. CMUCAD-88-27, June, 1988.Google Scholar
- [24]W. Maly and P. Nigh, “Built-in Current Testing-Feasibility Study,” Proceedings of the International Conference on Computer Aided Design, 1988.Google Scholar
- [25]V. K. Agarwal , E. Cerny, N. C. Rumin, Y. Savaria, and P. Schavan, “Techniques for Implementing Large-area Devices,” Proceedings of the International Conference on Computer Design, pp. 220–223, 1986.Google Scholar
- [26]C. Cyr , Y. Savaria, D. Audet, and J-L. Houle, “A Novel Self-Testing and Duration Scheme for Yield Improvement of Two Dimensional Logic Arrays,” Proceedings of the International Conference on Computer Design, pp. 494–500, New York, 1987.Google Scholar
- [27]W. Maly, “Design Methodology for Defect Tolerant Integrated Circuits,” Proceedings of the Custom Integrated Circuits Conference, pp. 27.5.1–27.5.4, Rochester, NY, May, 1988.Google Scholar
- [28]L. R. Carley and W. Maly, “A Circuit Breaker for Redundant IC Systems,” Proceedings of the Custom Integrated Circuits Conference, pp. 27.6.1–27.6.6, Rochester, NY, May, 1988.Google Scholar
- [29]M. W. Levi, “CMOS is Most Testable,” Proceedings of the International Test Conference, pp. 217–220, Washington, DC, September, 1981.Google Scholar
- [30]W. Maly, “Modeling of Lithography Related Losses for CAD of VLSI Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-4, pp. 166–177, 1985.CrossRefGoogle Scholar
- [31]C. F. Hawkins and J. M Soden, “Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs,” Proceedings of the International Test Conference, pp. 443–451, Washington, DC, September, 1986.Google Scholar
- [32]J. M. Acken, “Testing for Bridging Faults (Shorts) in CMOS Circuits,” Proceedings of the Design Automation Conference, pp. 717–718, Miami Beach, FL, 1983.Google Scholar
- [33]W. Maly, P. Nag, and P. Nigh, “Testing Oriented Analysis of CMOS ICs with Opens,” Proceedings of the International Conference on Computer Aided Design, 1988.Google Scholar
- [34]D. B. Feltham, P. Nigh, L. R. Carley, and W. Maly, “Current Sensing for Built-in Testing of CMOS Circuits,” Proceedings of the International Conference on Computer Design, 1988.Google Scholar