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Introduction

  • Patrick Dewilde
  • Zhen-Qui Ning
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 103)

Abstract

The aim of integrated circuit design is often to assemble as many devices as possible in a chip of silicon together with all the interconnects and driver circuits needed. Present day technology allows feature resolution in the neighborhood of 1 micron (=10−6m), moving downward to possibly 0.5 micron in the mid nineties. Very small device dimensions and proximity can be achieved resulting in high packing densities and “Ultra Large Scale Integration”. In addition to lateral size reduction, modern technology offers an increasing number of interconnect layers, starting from straps between the polysilicon interconnect layers and the so called “diffusion” paths in the silicon substrate, metal 1, metal 2 and possibly higher metal layers. This stacking of layers is made possible by advanced techniques of planarization.

Keywords

Threshold Voltage Parasitic Capacitance Microwave Theory Tech Exterior Problem Capacitance Coefficient 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1990

Authors and Affiliations

  • Patrick Dewilde
    • 1
  • Zhen-Qui Ning
    • 1
  1. 1.Delft University of TechnologyNetherlands

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