Abstract
This chapter considers the task of transforming dataflow program graphs into partitioned graphs, and thence into PML. Section 4.1 extends the work of Section 1.1 by completing the description of DFPG’s. Section 4.2 discusses the issues involved in generating partitioned code from DFPG’s. Section 4.3 presents the design of a suitable code generator.
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© 1990 Kluwer Academic Publishers
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Iannucci, R.A. (1990). Compiling for the Hybrid Architecture. In: Parallel Machines: Parallel Machine Languages. The Kluwer International Series in Engineering and Computer Science, vol 96. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1543-8_4
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DOI: https://doi.org/10.1007/978-1-4613-1543-8_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8827-5
Online ISBN: 978-1-4613-1543-8
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