Abstract
Logic circuits based on the enhancement-depletion inverter are simple in design and efficient in area and power. However, when the output is loaded with another stage, the maximum output voltage, V OH, limited to a value equal to the Schottky gate diode turn-on voltage, and the minimum output voltage, V OL, is often greater than the threshold voltage of the enhancement transistor of the following stage. As a result, the noise margins are often comparable to the threshold voltage, so if the latter changes, the noise margins could become unacceptably small.
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References
W.B. Leung, Y.K. Lo, Y.T. Oh, W.A. Oswald, E.K. Poon, C.E. Reid, L.E. Ackner, and T.C. Poon, “2K Gate circuits with 125ps Gate Delay Using GaAs HEMT Technology,” IEEE GaAs Integrated Circuits Symposium Technical Digest, 1989, pp. 57–60.
W.B. Leung, K.W. Teng, A.I. Faris, A.C. Hu, L.E. ACkner, C.E. Reid, and T.C. Poon, “3.5K Gate 32-Bit ALU Using GaAs HFET Technology.” Private communication.
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© 1990 Kluwer Academic Publishers
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Wing, O. (1990). Buffered ED Logic Circuits. In: Gallium Arsenide Digital Circuits. The Kluwer International Series in Engineering and Computer Science, vol 109. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1541-4_5
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DOI: https://doi.org/10.1007/978-1-4613-1541-4_5
Publisher Name: Springer, Boston, MA
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