The Cost of TLB Consistency
When paged virtual memory is supported as part of the memory hierarchy in a shared-memory multiprocessor system, translation-lookaside buffers (TLBs) are often used to cache copies of virtual-to-physical address translation information. This translation information is also stored in data structures called page tables. Since there can be multiple images of the translation information for a page accessible by processors, the modification of one image can result in inconsistency among the other images stored in TLBs and the page table. This TLB consistency problem can cause a processor to use stale translation information, which may result in incorrect program execution.
TLB consistency-ensuring management carries with it performance overhead. This cost is manifested in the processor time attributable, either explicitly or implicitly, to the adopted solution. Some solutions to this problem have been shown to be effective in small-scale multiprocessor systems but are not likely to be satisfactory for large-scale systems. In the absence of performance data, this paper examines performance costs associated with solutions to the TLB consistency problem and endeavors to delineate those characteristics of solutions that are desirable in terms of performance in large-scale systems.
enlist the participation of a processor only when it will use inconsistent information,
place necessary locks on the smallest possible data entities,
not introduce serialization,
keep extra communication to a minimum, and
have an insignificant impact on network traffic.
Two solutions are described that meet the first four criteria but that may have an impact on network traffic.
KeywordsNetwork Traffic Multiprocessor System Memory Hierarchy Virtual Memory Page Fault
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