Abstract
A major difficulty in rapid prototyping digital signal processing systems is the interconnection of processors with tailored networks. This difficulty can be alleviated by utilizing a standardized processor-to-processor interface. This approach permits the configuration of application specific hardware, with arbitrary hardware redundancy, to match the signal flow graph of specific applications. The hardware is mapped to the application as opposed to the traditional approach of mapping the application to the hardware. An inventory of heterogeneous processors, specialized to perform a predefined set of functions, enables rapid prototyping of systems with arbitrary topologies and functionalities. Application specific systems that match the signal flow graph of applications outperform general purpose systems both in speed and throughput.
This research focuses on solving the problems associated with the interconnection of the heterogeneous building blocks into systems with arbitrary topologies. A communication architecture is proposed that allows the interconnection of processors with varying speed and functionalities. Standardization of the Interface Control Unit (ICU) greatly reduces the development cost and time by removing the need to design and develop custom interfaces.
A robust event transaction protocol has been developed which eliminates centralized control and synchronization. The communication protocol is designed to be self-organizing and self-synchronizing by distributing control functions among the individual system resources through the Interface Control Unit (lCU). The protocol is optimized and verified by simulation using Rainbow Nets. Using this approach, it is possible to investigate variables in system configuration, application algorithms, and VLSI technology parameters separately. A gate-level synchronous design of the ICU is developed using LSI Logic Inc., LCA300K Technology. This is a CMOS technology with a minimum feature size of 0.7 micron.
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References
R. R. Shively, et al., “A High Performance Reconfigurable Architecture,” Proceedings Super computing Conference, Reno, Nevada, November 1989, pp. 505–509.
“An Outline Protocol Specification for an Interface Control Unit (ICU),” GEC Internal Document No. P910/9234, June 1992.
M. A. Schoenfelder, The Design and Implementations of Rainbow Net Simulator with Dependability Modeling Applications, Masters Thesis, University of Texas at Austin, 1990.
A. M. Johnson and M. A. Schoenfelder, “Rainbow Net Analysis of VAX cluster System Availability,” IEEE Transactions on Reliability, June 1991, pp. 226–236.
M. L. Fuccio, et al., “The DSP 32C: AT&T’s Second-Generation Floating- Point Digital Signal Processor,” IEEE Micro, December 1988, pp. 30–48.
M. J. Knudsen, “MUSEC, A Powerful Network of Signal Microprocessors,” Proc. 1983 IEEE International Conference on Acoustics, Speech and Signal Processing, Boston, pp. 431–434.
Brent Baxter, et al., “Building Blocks for a New Generation of Application Specific Computing Systems,” 1990 International Conference On Application Specific Array Processors, Princeton, New Jersey, Sept. 5–7 1990, pp. 190–201.
C. Whitby-Strevens, “The Transputer,” Proceedings of the 12th International Symposium on Computer Architecture, Boston, MA, June, 1985, Vol. 13, No. 3, pp. 292–300.
W. J. Dally and C. L. Seitz, “The Torus Routing Chip,” Journal of Distributed Computing, 1986, Vol. 1, No. 3.
W. A. Clark, “Macromodular Computer Systems,” 1967 SJCC Proceedings, pp. 335–336.
S. M. Ornstein, et al., “A Functional Description of Macromodules,” 1967 SJCC Proceedings, pp. 337–355.
C. E. Molnar, et al., “The CHASM: A Macromodular Computer for Analyzing Neuron Models,”1967 SJCC Proceedings, pp. 393–396.
R. G. Cooper, “Micromodules: Microprgrammable Building Blocks For Hardware Development,” Proceedings of the First Annual Symposium on Computer Architecture 1974, pp. 221–226.
R. M. Keller, “Towards A Theory of Universal Speed-Independent Modules,” IEEE Transactions on Computers, January 1974, pp. 21–33.
T. E. Curtis, “A Modular Approach to Signal Processing,” Proc. Real-Time General-Purpose, High-Speed Signal Processing Systems for Underwater Research, SACLANT ASW Research Centre, La Spezia, Italy, Publication CP-25 (Dec. 1979).
Y. S. Wu, “A Common Operational Software (ACOS) Approach to a Signal Processing Development System,” Proc. 1983 IEEE International Conference on Acoustics, Speech and Signal Processing, Boston, pp. 1172–1175.
Y. S. Wu, et al., “Architectural Approach to Alternate Low-level Primitive Structures (ALPS) for Acoustic Signal Processing,” IEE Proceedings, Vol. 131, Part F, 1984, pp. 327–333.
Y. S. Wu and Les J. Wu, “Signal Flow: A VLSI Fault Tolerant Architecture for Signal Processing,” VLSI 85, Tokyo, August 26–28, 1985, pp. 223–232.
Mohammad S. Khan, Design of an Interface Control Unit for Rapid Prototyping, Ph.D. Dissertation, University of Texas at Austin, 1995.
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© 1997 Kluwer Academic Publishers
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Khan, M.S. (1997). Design and Implementation of an Interface Control Unit for Rapid Prototyping. In: Swartzlander, E.E. (eds) Application Specific Processors. The Kluwer International Series in Engineering and Computer Science, vol 380. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1457-8_8
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DOI: https://doi.org/10.1007/978-1-4613-1457-8_8
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