Advertisement

A Unified View of CORDIC Processor Design

  • Shaoyun Wang
  • Vincenzo Piuri
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 380)

Abstract

The COordinate Rotation Digital Computer (CORDIC) algorithm is a well-known and widely studied method for plane vector manipulation. It uses a sequence of partial vector rotations to approximate the expected one. Under different operating modes, this algorithm can be used either to do Givens transformation for vector rotation and vectoring or to evaluate more than a dozen of elementary, trigonometric, and hyperbolic functions. CORDIC processors are therefore powerful computing systems for applications involving large amount of rotation operations and mathematical functions mentioned above.

CORDIC computation adopts only primitive arithmetic operations (additions, subtractions, and shiftings) instead of multiplications. This has a great impact on the hardware characteristics especially when circuit complexity is concerned. As a consequence, the CORDIC algorithm is become a widely used approach for elementary function evaluation whenever the silicon area is a primary constraint. The main drawback is the intrinsic low performance due to the iterative computational approach. In particular, parallelism cannot be easily introduced since each CORDIC iteration has to select the rotation direction by analyzing the result of the previous one.

In this chapter, a unified view of the CORDIC architecture design is presented. Our goal is to provide a wide spectrum of architectures, a coordinated and comprehensive design methodology, and the main figures of merit characterizing performance and complexity. This methodology contains the basic guidelines for designers to choose an approach with respect to specific requirements and constraints of the application.

Keywords

Singular Value Decomposition Clock Cycle Pipeline Stage Circuit Complexity Computer Arithmetic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 5-1.
    J. Voider, “The CORDIC Trigonometric Computing Technique,”IRE Transactions on Electronic Computers, Vol. EC-8, pp. 330–334, 1959.CrossRefGoogle Scholar
  2. 5-2.
    J. Walther, “A Unified Algorithm For Elementary Functions,” Spring Joint Computer Conference Proceedings, Vol. 38, pp. 379–385, 1971.Google Scholar
  3. 5-3.
    Y. Hu and H. Lian., “CALF: a CORDIC Adaptive Lattice Filter,” IEEE Transactions on Signal Processing, Vol. 40, pp. 990–993, 1992.CrossRefGoogle Scholar
  4. 5-4.
    P. Regalia and P. Loubaton, “Rational Subspace Estimation Using Adaptive Lossless Filters,” IEEE Transactions on Signal Processing, Vol. 40, pp. 2392–2405, 1992.MATHCrossRefGoogle Scholar
  5. 5-5.
    H. Hahn, B. Hosticka, and D. Timmermann, “Alternative Signal Processor Arithmetic for Modified Implementation of a Normalised Adaptive Channel Equaliser,” IEE Proceedings. Part F, Radar and Signal Processing, Vol. 139, pp. 36–42, 1992.CrossRefGoogle Scholar
  6. 5-6.
    A. Despain, “Fourier Transform Computations Using CORDIC Iterations,” IEEE Transactions on Computers, Vol. C-23, pp.993–1001, 1974.CrossRefGoogle Scholar
  7. 5-7.
    A. Despain, “Very Fast Fourier Transform Algorithm for Hardware Implementation,” IEEE Transactions on Computers, Vol. C-28, pp. 333–341, 1979.MathSciNetCrossRefGoogle Scholar
  8. 5-8.
    Y. Hu and S. Naganathan, “An Angle Recoding Method for CORDIC Algorithm Implementation,” IEEE Transactions on Computers, Vol. 42, pp. 99–102, 1993.CrossRefGoogle Scholar
  9. 5-9.
    Y. Hu and S. Naganathan, “A Novel Implementation of Chirp Z-Transformation Using a CORDIC Processor,” IEEE Transactions on ASSP, Vol. 38, pp. 352–354, 1990.CrossRefGoogle Scholar
  10. 5-10.
    D. Timmermann, H. Hahn, and B. Hosticka, “Hough Transform Using CORDIC Method,” Electronics Letters, Vol. 25, pp. 105–206, 1989.CrossRefGoogle Scholar
  11. 5-11.
    J. Lee and T. Lang, “Floating Point Implementation of Redundant CORDIC for QR Decomposition,” Technical Report #CSD-890044, Department of Computer Science, UCLA, 1989.Google Scholar
  12. 5-12.
    L. Chang and S. Lee, “Systolic Arrays for the Discrete Hartley transform,” IEEE Transactions on Signal Processing, Vol. 39, pp. 2411–2418, 1991.MATHCrossRefGoogle Scholar
  13. 5-13.
    K. Jones, “Parallel DFT Computation on Bit-serial Systolic Processor Arrays,” IEE Proceedings. Part E, Computers and Digital Techniques, Vol. 140, pp. 10–18, 1993.CrossRefGoogle Scholar
  14. 5-14.
    S. Wang and E. E. Swartzlander, Jr., “Critically Damped CORDIC Algorithm”, Proceedings of the 37th Midwest Symposium on Circuits and Systems, Lafayette, LA, pp. 253–256, August 1994.Google Scholar
  15. 5-15.
    J. Cavallaro and A. Elster, “Complex Matrix Factorizations with CORDIC Arithmetic,” Technical Report 89–1071, Department of Computer Science, Cornell University, 1989.Google Scholar
  16. 5-16.
    J. Cavallaro and F. Luk, “Architectures for a CORDIC SVD Processor,” Proc. SPIE, Real Time Signal Processing IX, Vol. 698, pp. 45–53, 1986.Google Scholar
  17. 5-17.
    J. Cavallaro and F. Luk, “CORDIC Arithmetic for an SVD Processor,” Proceeding of the 8th Symposium on Computer Arithmetic, Como, Italy, pp. 113–120, 1987 and Journal of Parallel and Distributed Computing, Vol. 5, pp. 271–290, 1988.CrossRefGoogle Scholar
  18. 5-18.
    C. Shelin, “Calculator Function Approximation,”Amer. Math. Monthly, Vol. 90, No. 5, May 1983.Google Scholar
  19. 5-19.
    J. Muller, “Discrete Basis and Computation of Elementary Functions,” IEEE Transactions on Computers, Vol. C-34, pp. 857–862, 1985.CrossRefGoogle Scholar
  20. 5-20.
    J. Delosme, “CORDIC Algorithms: Theory and Extensions,” Proc. SPIE, Vol. 1152, pp. 131–145, 1989.Google Scholar
  21. 5-21.
    H. Hsiao and J. Delosme, “The CORDIC Householder Algorithm,” Proceedings of the 10th Symposium on Computer Arithmetic, pp. 256–263, 1991.Google Scholar
  22. 5-22.
    C. Mazenc, X. Merrheim, and J. Muller, “Computing Functions arccos and arcsin Using CORDIC,” IEEE Transactions on Computers, Vol. 42, pp. 99–102, 1993.CrossRefGoogle Scholar
  23. 5-23.
    K. Kota and J. Cavallaro, “Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processor,” IEEE Transactions on Computers, Vol. 42, pp. 769–779, 1993.CrossRefGoogle Scholar
  24. 5-24.
    Y. Hu, “The Quantization Effects of the CORDIC Algorithm,” IEEE Transactions on Signal Processing, Vol. 40, 1992, pp. 834–844.MATHCrossRefGoogle Scholar
  25. 5-25.
    D. Cochran, “Algorithms and Accuracy in the HP35,” Hewlett Packard Journal, Vol. 23, 1972, pp. 10–11.Google Scholar
  26. 5-26.
    T. Curtis, P. Allison, and J. Howard, “A CORDIC Processor for Laser Trimming,” IEEE Micro, Vol. 6, pp. 61–71, June 1986.CrossRefGoogle Scholar
  27. 5-27.
    M. Cosnard, A. Guyot, B. Hochet, J. Muller, H. Ouaouicha, P. Paul, and E. Aysman, “The FELIN Arithmetic Processor Chip”, Proceedings of the 8th Symposium on Computer Arithmetic, pp. 107–112, 1987.Google Scholar
  28. 5-28.
    P. Chown, “Notes on the Design of a Barrel Shifter for the Warwick Pipelined CORDIC,” Research Report #161, Department of Computer Science, University of Warwick, Coventry CV4 7AL, UK, 1990.Google Scholar
  29. 5-29.
    P. Chown, “VLSI Design of a Pipelined CORDIC Processor,” Research Report #164, Department of Computer Science, University of Warwick, Coventry CV4 7AL, UK, 1990.Google Scholar
  30. 5-30.
    D. Timmermann, H. Hahn, and B. Hosticka, “A programmable CORDIC chip for digital signal processing applications,”IEEE Journal of Solid-State Circuits, Vol. 26, pp. 1317–1321, 1991.CrossRefGoogle Scholar
  31. 5-31.
    I. Koren and O. Zinaty, “Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations,” IEEE Transactions on Computers, Vol. 39, pp. 1030–1037, 1990.CrossRefGoogle Scholar
  32. 5-32.
    G. Hekstra and E. Deprettere, “Floating Point CORDIC,” Proceedings of the 11th Symposium on Computer Arithmetic, pp. 130–137, 1993.Google Scholar
  33. 5-33.
    N. Hemkumar and J. Cavallaro, “Efficient Complex Matrix Transformations with CORDIC,” Proceedings of the 11th Symposium on Computer Arithmetic, pp. 122–129, 1993.Google Scholar
  34. 5-34.
    R. Kundmund and et al., “CORDIC Processor with Carry Save Architecture,” Proceeding of the 1990 European Solid State Circuits Conference, Grenoble, Sept. 1990, pp. 193–196.Google Scholar
  35. 5-35.
    D. Timmermann, H. Hahn, and H. Hosticka, “Low Latency Time CORDIC Algorithms,” IEEE Transactions on Computers, Vol. 41, 1992, pp. 1010–1015.CrossRefGoogle Scholar
  36. 5-36.
    E. Deprettere, P. Dewilde, and U. Udo, “Pipelined CORDIC Architectures for Fast VLSI Filtering and Array Processing,” IEEE Transactions on Signal Processing, Vol. 40, 1992, pp. 834–844.CrossRefGoogle Scholar
  37. 5-37.
    H. Dawid and H. Meyr, “High Speed Bit-level Pipelined Architectures for Redundant CORDIC Implementation,” Proceedings of the 1992 International Conference on Application-Specific Array Processors, Berkeley, CA, pp. 358–372, 1992.Google Scholar
  38. 5-38.
    E. Antelo, J. Bruguera, J. Villalba, and E. Zapata, “Redundant CORDIC Rotator Based on Parallel Prediction,” Proceedings of the 12th International Symposium on Computer Arithmetic, Bath, UK, pp. 172–1791, July 1995.Google Scholar
  39. 5-39.
    M. Andrews and D. Eggerding, “A Pipelined Computer Architecture for Unified Elementary Function Evaluation,” Computer Electronic Engineering, Vol. 5, 1978, pp. 189–202.MATHCrossRefGoogle Scholar
  40. 5-40.
    J. Delosme, “VLSI Implementation of Rotations in Pseudo Euclidean Spaces,” Proceedings of the IEEE International Conference on Acoustic, Speech, and Signal Processing, Vol. 2, 1983, pp. 927–930.Google Scholar
  41. 5-41.
    T. Sung, T. Parng, Y. Hu, and P. Chou, “Design and Implementation of a VLSI CORDIC Processor,” Proceedings of the 1986 International Symposium on Circuits and Systems, Vol. 3, 1986, pp. 934–935.Google Scholar
  42. 5-42.
    J. Cavallaro and F. Luk, “CORDIC Arithmetic for an SVD Processor,” Proceeding of the 8th Symposium on Circuits and Systems, 1988, pp. 2043–2047.Google Scholar
  43. 5-43.
    A. de Lange, A. van der Hoeven, E. Deprettere, and J. Bu, “An Optimal Floating-Point Pipeline CMOS CORDIC Processor,” Proceeding of the 1988 IEEE International Symposium on Circuits and Systems, 1989, pp. 2043–2047.Google Scholar
  44. 5-44.
    R. Harber, J. Li, X. Xu, and S. Bass, “Bit-Serial CORDIC Circuits for Use in a VLSI Silicon Compiler,” Proceedings of the 1989 IEEE International Symposium on Circuits and Systems, Vol. 1, 1989, pp.154–157.CrossRefGoogle Scholar
  45. 5-45.
    A. de Lange and E. Deprettere, “Design and Implementation of a Floating-Point Quasi-Systolic General Purpose CORDIC Rotator for High-Rate Parallel Data and Signal Processing,” Proceeding of the 10th Symposium on Computer Arithmetic, 1991, pp. 272–281.Google Scholar
  46. 5-46.
    J. Delosme and S. Hsiao, “CORDIC Algorithms in Four Dimensions,” Proceedings of SPIE - The International Society for Optical Engineering, Vol. 1348, San Diego, CA, pp. 349–360, July 1990.5–47.Google Scholar
  47. 5-47.
    S. Wang and E. E. Swartzlander, Jr., “Merged CORDIC Algorithm,” Proceedings of the IEEE 1995 International Symposium on Circuits and Systems, Seattle, WA, pp. 1988–1991, April 1995.Google Scholar
  48. 5-48.
    N. Takagi, T. Asada, and S. Yajima, “Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation,” IEEE Transactions on Computers, Vol. 40, 1991, pp.989–995.MathSciNetCrossRefGoogle Scholar
  49. 49.
    J. Duprat and J. Muller, “The CORDIC Algorithm: New Results for Fast VLSI Implementation,” IEEE Transactions on Computers, Vol. 42, pp. 168–178, 1993.CrossRefGoogle Scholar
  50. 5-50.
    M. Ercegovac and T. Lang, “On the Fly Conversions of Redundant into Conventional Representations,” IEEE Transactions on Computers, Vol. C-36, pp. 895–897, 1987.CrossRefGoogle Scholar
  51. 5-51.
    M. Ercegovac and T. Lang, “Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD,” IEEE Transactions on Computers, Vol. 39, 1990, pp. 725–740.CrossRefGoogle Scholar
  52. 5-52.
    J. Lee and T. Lang, “SVD by Constant Factor-Redundant-CORDIC,” Proceedings 10th Symposium on Computer Arithmetic, Grenoble, France, pp. 264–271, 1991.Google Scholar
  53. 5-53.
    J. Lee and T. Lang, “Constant-Factor Redundant CORDIC for Angle Calculation and Rotation,” IEEE Transactions on Computers, Vol. 41, pp. 1016–1025, 1992.CrossRefGoogle Scholar
  54. 5-54.
    H. Lin and H. Sips, “On-Line CORDIC Algorithms,” IEEE Transactions on Computers, Vol. 39, pp. 1030–1037, 1990.CrossRefGoogle Scholar
  55. 5-55.
    P. Tu and M. Ercegovac, “Application of On-Line Arithmetic Algorithms to the SVD Computation: Preliminary Results,” Proceedings of the 10th Symposium on Computer Arithmetic, pp. 246–255, 1991.Google Scholar
  56. 5-56.
    S. Wang, V. Piuri, and E. E. Swartzlander, Jr., “A Unified View of CORDIC Processor Design,” Proc. The 39th Midwest Symposium on Circuits and Sytems, Ames, IA, August 1996.Google Scholar
  57. 5-57.
    S. Wang, V. Piuri, and E. E. Swartzlander, Jr., “Granularly-Pipelined CORDIC Processor for Sine and Cosine Generators,” Proc. IEEE International Conference on Acoustics, Speech and Signal Processing, Vol. 6, pp. 3299–3302, Atlanta, Georgia, May 1996.Google Scholar

Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Shaoyun Wang
    • 1
  • Vincenzo Piuri
    • 2
  1. 1.Crystal Semiconductor CorporationAustinUSA
  2. 2.Department of Electronics and InformationPolitecnico di MilanoMilanoItaly

Personalised recommendations