Design for Testability

  • Pran Kurup
  • Taher Abbasi


The ever-increasing density of ASICs, the whole-sale switch to surface-mount technology, and the growing interest in multi-chip modules (MCM), have resulted in testable designs becoming a greater priority. Thus far, designers have considered testability as an issue which comes into play at the very end of the design cycle. However, in the ASIC design flow based on synthesis, it is essential that designers develop a test strategy and address testability issues concurrently with other activities in the design cycle. In this chapter, Test Synthesis and Automatic Test Pattern Generation (ATPG) using the Synopsys Test Compiler (TC) are discussed.


Test Pattern Test Vector Fault Coverage Automatic Test Pattern Generation Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Test Compiler Reference ManualGoogle Scholar
  2. 2.
    Test Compiler Streamlined Methodology Application NoteGoogle Scholar
  3. 3.
    Synopsys Newsletter “Impact” Support Center Q&AGoogle Scholar

Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Pran Kurup
    • 1
  • Taher Abbasi
    • 2
  1. 1.Cirrus Logic, IncUSA
  2. 2.Synopsys, IncUSA

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