Constraining and Optimizing Designs — II

Abstract

This chapter is a continuation of logic synthesis strategies using DC. First, FSM synthesis steps are outlined using examples from Chapter 2. Then, the tips for FSM synthesis are provided. This is followed by a discussion on fixing min_delay violations during synthesis. One of the biggest advantages of logic synthesis is the ability to target different technology libraries. Technology translation is discussed and the steps involved in translating designs with black-boxes are outlined. Finally, a number of classic scenarios have been discussed.