• Mohamed S. Ben Romdhane
  • Vijay K. Madisetti
  • John W. Hines
Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 367)


This chapter reviews the background required for this monograph. First, common ASIC design approaches are introduced. Advantages and limitations of ASICs with regard to general-purpose DSP processors are outlined. Section 2.2 describes popular design approaches and environments proposed in recent literature to synthesize ASICs form HDL descriptions. In section 2.3, a comparison between existing ASIC design tools is proposed based on criteria such as — design turnaround, flexibility, ease-of-use, and performance. Section 2.4 introduces a cost model originally proposed by Synopsys and Xilinx that compares the ASIC and FPGA alternatives. This cost model and assumptions made will serve us later, when we compare our proposed design methodology with other high-level approaches.


Field Programmable Gate Array Register Transfer Level Macro Cell Data Flow Graph Product Lifetime 
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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Mohamed S. Ben Romdhane
    • 1
  • Vijay K. Madisetti
    • 2
  • John W. Hines
    • 3
  1. 1.Rockwell International CorporationUSA
  2. 2.Georgia Institute of Technology & VP TechnologiesUSA
  3. 3.US Air Force Wright LaboratoriesUSA

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