Abstract
As indicated in Chapter 2, the main shortcoming of the disk model was its inability to model faults starting from the actual failure mechanism, rather than from the spot defect level. It was also observed in the model validation experiment [1], [2], [3] and in the experiment described in [4] that most failures in ICs were caused by contamination which deposited on the IC during some processing step. To increase the fidelity of modeling, therefore, it is essential to begin all fault and yield model studies/simulations at the contamination level.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Khare, W. Maly, S. Griep and D. Schmitt-Landsiedel, “Yield-Oriented Computer-Aided Defect Diagnosis,” IEEE Transactions on Semiconductor Manufacturing, vol. 8, no. 2, pp. 195–206, May 1995.
J. Khare, S. Griep, W. Maly, and D. Schmitt-Landsiedel, “SRAM-based Extraction of Defect Characteristics,” Proceedings of the 1994 International Conference on Microelectronic Test Structures, pp. 98–107, San Diego, March 1994.
J. Khare, S. Griep, H. -D. Oberle, D. Schmitt-Landsiedel, W. Maly, U. Kollmer and D. M. H. Walker, “Key Attributes of an SRAM Testing Strategy Required for Effective Process Monitoring,” Proceedings of the 1993 International Workshop on Memory Testing, pp. 84–89, San Jose, August 1993.
J. Khare, W. Maly and M. Thomas, “Extraction of Defect Size Distributions in an IC Layer using Test Structure Data,” IEEE Transactions on Semiconductor Manufacturing, vol. 7, no. 3, pp. 354–368, August 1994.
C. H. Stapper, I. M. Armstrong and K. Saj, “Integrated Circuit Yield Statistics,” IEEE Proceedings, vol. 71, April 1993.
C. H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities,” IBM Journal of Research and Development, vol. 27 no. 6, pp. 549–557, November 1983.
A. V. Ferris-Prabhu, “Defect Size Variations and Their Effect on the Critical Area of VLSI Devices,” IEEE Journal of Solid-State Circuits, vol. 20 no. 4, pp. 878–880, August 1985.
A. V. Ferris-Prabhu, “Role of Defect Size Distribution in Yield Modeling,” IEEE Transactions on Electron Devices, vol. 32 no. 9, pp. 1727–1736, September 1985.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1996 Kluwer Academic Publishers
About this chapter
Cite this chapter
Khare, J.B., Maly, W. (1996). Contamination-Defect-Fault (CDF) Simulation. In: From Contamination to Defects, Faults and Yield Loss. Frontiers in Electronic Testing, vol 5. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1377-9_3
Download citation
DOI: https://doi.org/10.1007/978-1-4613-1377-9_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8595-3
Online ISBN: 978-1-4613-1377-9
eBook Packages: Springer Book Archive