Logic verification refers to verifying the correctness of a logic design before fabrication or even before any detailed physical design. It is motivated by the fact that changes and modifications in a large circuit are expensive, difficult and time-consuming. Therefore, throughout the design process, verification is done at various design levels and stages to ensure that every step in the design meets its objectives and requirements. Logic verification is usually employed at the end of the logic design phase.
KeywordsTest Generation Truth Table Very Large Scale Integration Combinational Logic Logic Design
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