Abstract
Most modern logic simulators handle the problems specific to MOS integrated circuits by including the notion of signal strength in the logic model. However, the use of strength does not, by itself, solve all the modeling problems inherent to MOS circuits. For example, circuit designers use many combinations of transistors which do not have a direct mapping to a logic gate and therefore cannot be represented conveniently at the gate level. It is also difficult to model the logic operation of dynamic circuits in a convenient form in a standard logic simulator. Transfer gates further complicate the situation because they introduce dynamic loading effects, bidirectional signal flow, and capacitive charge-sharing effects. Many of these problems were resolved with the advent of the switch-level modeling and simulation technique [BRY80].
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© 1990 Kluwer Academic Publishers
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Saleh, R.A., Newton, A.R. (1990). Switch-Level Timing Simulation. In: Mixed-Mode Simulation. The Kluwer International Series in Engineering and Computer Science, vol 98. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-0695-5_6
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DOI: https://doi.org/10.1007/978-1-4613-0695-5_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4612-8030-9
Online ISBN: 978-1-4613-0695-5
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