A Unified Approach to the Performance Evaluation of Multiprocessors

  • E. Sanvicente
  • M. A. Fiol
  • J. L. Melús


This paper introduces a unified approach to approximately compute the bandwidth of tightly coupled multiprocessors, working either synchronously or asynchronously. Several types of interconnection networks are considered, namely: crossbar, multiple-bus and multiple-bus with partial-busses. The analysis is carried out for both constant and exponential memory service times. Simulation runs are also included to validate the approximation used in the model. Although the analysis is asymptotic, the computations turn out to be quite accurate for moderate, or even small, system sizes.


Interconnection Network Markov Chain Model Memory Module Multiprocessor System Service Completion 
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  1. [1]
    D.P. Bhandarkar, “Analysis of memory interference in multiprocessors”, IEEE Trans. Comput., vol. 024, pp. 897–908, Sep. 1975.CrossRefGoogle Scholar
  2. [2]
    F. Baskett and A.J. Smith, “Interference in multiprocessor computer systems with interleaved memory”, Comm, of the ACM, vol. 19, pp. 327–334, Jun. 1976.CrossRefGoogle Scholar
  3. [3]
    M. Valero, J.M. Llaberia, J. Labarta, E. Sanvicente and T. Lang, “A performance evaluation of the multiple bus network for multiprocessor systems”, Proc. 1983 ACM Sigmetrics Conf., Minneapolis, USA, pp. 200–206, Aug. 1983.Google Scholar
  4. [4]
    K. B. Irani and I.H. Önyüksel, “A closed-form solution for the performance analysis of multiple-bus multiprocessor systems”, IEEE Trans. Comput., vol. C-33, pp. 1004–1012, Nov. 1984.CrossRefGoogle Scholar
  5. [5]
    M. A. Marsan and M. Gerla, “Markov models for multiple bus multiprocessor systems”, IEEE Trans. Comput., vol. C-31, pp. 239–248, Mar. 1982.CrossRefGoogle Scholar
  6. [6]
    T. Lang, M. Valero and I. Alegre.. “Bandwidth of crossbar and multiple-bus connections for multiprocessors”, IEEE Trans. Comput., vol. C-31, pp. 1227–1234, Dec. 1982.CrossRefGoogle Scholar
  7. [7]
    D. P. Bhandarkar, “Markov chain models for analyzing memory interference in multiprocessor computer systems”, Proc. I Ann. Symp. Comp. Architecture, pp. 1–6, Dec. 1973.Google Scholar
  8. [8]
    Y.-C. Liu and C.-J. Jou, Effective memory bandwidth and processor blocking probability in multiple-bus systems, IEEE Trans. Comput., vol. C-3B, pp. 761–764, Jun. 1987.Google Scholar

Copyright information

© Plenum Press, New York 1989

Authors and Affiliations

  • E. Sanvicente
    • 1
  • M. A. Fiol
    • 1
  • J. L. Melús
    • 1
  1. 1.Dep. de Matemàtica Aplicada i TelemàticaUniversitat Politècnica de CatalunyaBarcelonaSpain

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