Layout complexity of bit-permuting exchanges in multi-stage interconnection networks

Part of the Network Theory and Applications book series (NETA, volume 5)


The layout area of a multi-stage interconnection network of 2 × 2 elements is normally dominated by the inter-stage connection wires rather than the elements. We treat the VLSI layout of an inter-stage exchange pattern as a channel routing problem under the popular two-layer Manhattan model. The layout complexity of an exchange pattern is defined in terms of the global density of the channel routing problem so as to reflect the layout area. We then determine the layout complexity for all bit-permuting exchanges. The result leads to the generalization of the layout optimality of divide-and-conquer networks.


Binary Sequence Layout Optimality Global Density Disjoint Copy Vertical Line Segment 
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  1. [1]
    D.P. Agrawal, Graph theoretical analysis and design of multistage interconnection Networks, IEEE Trans. Computers, Vol. C-32, no.7, pp. 637–648, July, 1983.CrossRefGoogle Scholar
  2. [2]
    K. E. Batcher, Sorting networks and their applications, Proc. of AFIP 1968 Spring Joint Computer Conf., Vol. 32, pp. 307–314, 1968.Google Scholar
  3. [3]
    K. E. Batcher, The flip network in STARAN, Proc. 1976 Int. Conf. Parallel Processing, pp. 65–71.Google Scholar
  4. [4]
    H. Burchardt and L. C. Barbosa, Contributions to the Application of the Viterbi Algorithm, IEEE Trans. Information Theory, Vol. 31, pp. 626–634, 1985.CrossRefGoogle Scholar
  5. [5]
    J. B. Dennis, Data Flow Supercomputer, Computers, Vol. 13, No. 11, pp. 48–56, Nov.1980.CrossRefGoogle Scholar
  6. [6]
    L. R. Goke and G. J. Lipovski, Banyan Networks for Partitioning Multiprocessing Systems, Proc. First Annual Computer Architecture Conf., pp. 21–28, Dec. 1973.Google Scholar
  7. [7]
    A. Huang and S. Knauer, Starlite: a wideband digital switch, Proceedings of GLOBECOM’84, pp. 121–125, 1984.Google Scholar
  8. [8]
    H. S. Kim and A. Leon-Garcia, Nonblocking property of reverse banyan networks, IEEE Trans. Commun., Vol. 40, No 3, pp. 472–476, March 1992.CrossRefGoogle Scholar
  9. [9]
    D. E. Knuth, The Art of Computer Programming, Volume 3, Addison-Wesley, 1973.Google Scholar
  10. [10]
    D. H. Lawrie, Access and Alignment of Data in an Array Processor, IEEE Trans. Computers, Vol. C-24, No. 12, pp. 1145–1155, Dec. 1975.MathSciNetCrossRefGoogle Scholar
  11. [11]
    S.-Y. R. Li, Formalization of Self-route Networks and the Rotary Switch, Proc.INFOCOM’94, pp. 438–446, Toronto, June 1994.Google Scholar
  12. [12]
    S.-Y. R. Li, Partial Sorting and Concentration by Parallel Networks, Proc. of International Workshop on Discrete Mathematics and Algorithms, pp. 27–43, 1994.Google Scholar
  13. [13]
    S.-Y. R. Li, and C. M. Lau, Concentrators in ATM Switching, Computer Systems Science and Engineering, (11) (6) (1996), pp. 335–342.zbMATHGoogle Scholar
  14. [14]
    S.-Y. R. Li, and W. Lam, ATM Switching by Divide-and-conquer interconnection of Partial Sorters, Microprocessors and Microsystems22 (1999), pp. 579–587.CrossRefGoogle Scholar
  15. [15]
    S.-Y. R. Li, G. M. Koo and H. Li, An algorithm for the construction of concentrators from 2 × 2 sorters, American Mathematical Society, DI-MA CS series in Discrete Mathematics and Theoretical Computer Science, Vol. 42, (1998), pp. 197–219.MathSciNetGoogle Scholar
  16. [16]
    S.-Y. R. Li and H. Li, Optimization in the fast knockout algorithm for self-route concentration, IEEE Proceedings of ICC’98, pp. 630–634, Atlanta, June,1998.Google Scholar
  17. [17]
    S.-Y. R. Li, Optimal multi-stage interconnection by divide-and-conquer networks, Proc. of the 2nd LASTED International Conference on Parallel and Distributed Computing and Networks, pp. 318–323, Brisbane, Australia, Dec.1998.Google Scholar
  18. [18]
    S.-Y. R. Li, H. Li and G. M. Koo, Fast knockout algorithm for self-route concentration, Computer Communications22 (1999), pp. 1574–1584.CrossRefGoogle Scholar
  19. [19]
    S.-Y. R. Li, Switching Networks: Algebraic Principles and Broadband Applications, book under preparing for Academic Press. Summer 2000.Google Scholar
  20. [20]
    S. F. Lundstrom and G. Barnes, A Controllable MIMD Architecture, Proc. Int. Conf. Parallel Processing, pp. 19–27, 1980.Google Scholar
  21. [21]
    J. H. Patel, Processor-Memory Interconnections for Multiprocessors, Proc. Sixth Annual Symp. Computer Architecture, pp.168–177, April 1979.Google Scholar
  22. [22]
    D. S. Parker, Note on Shuffle/Exchange-Type Switching Networks, IEEE Trans. on Computers, Vol. C-29, No. 3, pp. 213–222, March 1980.CrossRefGoogle Scholar
  23. [23]
    M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI physical design, McGraw-Hill, 1996.Google Scholar
  24. [24]
    B. J. Smith, A Pipelined, Shared Resource MIMD computer, Proc. Int. Conf. Parallel Processing, pp. 6–8, 1978.Google Scholar
  25. [25]
    H. S. Stone, Parallel Processing with the Perfect Shuffle, IEEE Trans. Computers, Vol. 20, pp. 153–161, 1971.CrossRefzbMATHGoogle Scholar
  26. [26]
    F. A. Togago and T.C. Kwok, The Tandem Banyan Switching Fabric: A Simple High-Performance Fast Packet Switch, Proc. IEEE INFOCOM’91, Vol. 3, 11A. 2, pp. 1245–1253, 1991.Google Scholar
  27. [27]
    C.-L. Wu and T. Y. Feng, On a Class of Multistage Interconnection Networks, IEEE Trans. on Computers, Vol. C-29, No. 8, pp. 694–702, Aug. 1980.MathSciNetCrossRefGoogle Scholar
  28. [28]
    C.-L. Wu and T. Y. Feng, On a Distributed-Processor Communication Architecture, Proc. Compcon., pp.599–605, 1980.Google Scholar

Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  1. 1.Department of Information EngineeringThe Chinese University of Hong KongHong KongChina

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