Abstract
The layout area of a multi-stage interconnection network of 2 × 2 elements is normally dominated by the inter-stage connection wires rather than the elements. We treat the VLSI layout of an inter-stage exchange pattern as a channel routing problem under the popular two-layer Manhattan model. The layout complexity of an exchange pattern is defined in terms of the global density of the channel routing problem so as to reflect the layout area. We then determine the layout complexity for all bit-permuting exchanges. The result leads to the generalization of the layout optimality of divide-and-conquer networks.
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Li, SY.R., Li, H. (2001). Layout complexity of bit-permuting exchanges in multi-stage interconnection networks. In: Du, D.Z., Ngo, H.Q. (eds) Switching Networks: Recent Advances. Network Theory and Applications, vol 5. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-0281-0_12
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DOI: https://doi.org/10.1007/978-1-4613-0281-0_12
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