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Layout complexity of bit-permuting exchanges in multi-stage interconnection networks

Chapter
Part of the Network Theory and Applications book series (NETA, volume 5)

Abstract

The layout area of a multi-stage interconnection network of 2 × 2 elements is normally dominated by the inter-stage connection wires rather than the elements. We treat the VLSI layout of an inter-stage exchange pattern as a channel routing problem under the popular two-layer Manhattan model. The layout complexity of an exchange pattern is defined in terms of the global density of the channel routing problem so as to reflect the layout area. We then determine the layout complexity for all bit-permuting exchanges. The result leads to the generalization of the layout optimality of divide-and-conquer networks.

Keywords

Binary Sequence Layout Optimality Global Density Disjoint Copy Vertical Line Segment 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 2001

Authors and Affiliations

  1. 1.Department of Information EngineeringThe Chinese University of Hong KongHong KongChina

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