SCRAM Cache in Sun-4/110

Abstract

Most RISC computers, including SPARC-based ones, execute instructions at close to a single cycle per instruction. Most memory accesses also take a single clock cycle. The Sun-4/110 has a cycle time of 70 nanoseconds, which implies that the memory chips need an access time of about 40 nanoseconds to compensate for the delays in sending out addresses and providing setup time for the resulting data. To satisfy this speed require­ment, it is normally necessary to use fast static RAMs to implement a cache memory. Caches, as well as being expensive, are complex and difficult to design and can consume scarce board area. The Sun-4/110 has no cache memory and yet performs as well as if it had one, thus avoiding consider­able expense and complexity.