SPARC: An ASIC Solution for High-Performance Microprocessors
Sun Microsystems’ Scalable Processor Architecture (SPARC) defines a general purpose 32-bit processor architecture. It was designed to allow cost effective and high performance implementations across a range of technologies. The simple yet efficient nature of the architecture makes it possible to implement it in a short period of time. It also makes SPARC very attractive for implementation in ASIC technologies, without sacrificing high performance. Its first implementation has been done in Fujitsu’s C20K gate array, and is the first high performance microprocessor to be designed in an ASIC technology. This paper summarizes the architecture and its gate array implementation.
Sun Microsystems is working towards making SPARC a truly open, multi-vendor processor architecture. It has already been licensed to three semiconductor companies: Fujitsu Microelectronics, Cypress Semiconductor and Bipolar Integrated Technology. A number of system houses including AT&T and Xerox have announced their intent to use SPARC in future products. In addition, the semiconductor licensees have had a number of design wins.
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- [Agrawal88]A. Agrawal, E.W. Brown, J. Petolino, J. Peterson, “Design Considerations for a Bipolar Implementation of SPARC,” IEEE COMPCON 88.Google Scholar
- [Chu87]N. Chu, L. Poltrack, J. Bartlett, J. Friedland, A. MacRae, Sun Performance, Sun Microsystems, Inc., Mountain View, CA.Google Scholar
- [Dubois88]M. Dubois, C. Scheurich, & F. Briggs, “Synchronization, Coherence and Ordering of Events in Multiprocessors,” to appear in IEEE Com., February 1988.Google Scholar
- [Garner88]Robert Garner, Anant Agrawal, Faye Briggs, Emil W. Brown, David Hough, Bill Joy, Steve Kleiman, Steven Muchnick, Masood Namjoo, Dave Patterson, Joan Pendelton and Richard Tuck. “The Scalable Processor Architecture” (SPARC) IEEE COMPCON 88.Google Scholar
- [Katevenis83]M. Katevenis, Reduced Instruction Set Computer Architectures for VLSI, Ph.D. dissertation, Computer Science Div., Univ. of California, Berkeley, 1983. Also published by M.I.T. Press, Cambridge, MA.Google Scholar
- [Kleiman88]S. Kleiman & D. Williams, “SunOS on SPARC,” IEEE COMPCON 88.Google Scholar
- [Muchnick88]S. Muchnick, C. Aoki, V. Ghodssi, M. Helft, M. Lee, R. Tuck, D. Weaver, & A. Wu, “Optimizing Compilers for the SPARC Architecture: An Overview,” IEEE COMPCON 88.Google Scholar
- [Namjoo88]M. Namjoo, A. Agrawal, D. Jackson, Le Quach, “CMOS Gate Array Implementation of the SPARC Architecture,” IEEE COMPCON 88.Google Scholar
- [NamjCypr88]M. Namjoo, et al., “CMOS Custom Implementation of the SPARC Architecture,” IEEE COMPCON 88.Google Scholar
- [Patterson85]D. Patterson, “Reduced Instruction Set Computers,” CACM, vol. 28, no. 1, Jan. 1985.Google Scholar
- [Quach88]L. Quach & R. Chueh, “CMOS Gate Array Implementation of the SPARC Architecture,” IEEE COMPCON 88.Google Scholar
- [Schafir87]M. Schafir & A. Nguyen, Sun-4/200 Benchmarks, Sun Microsystems, Inc., Mountain View, CA.Google Scholar
- [SPARC87]The SPARC Architecture Manual, Sun Microsystems, Inc., Mountain View, CA. Also published by Fujitsu Microelectronics, Inc., 3320 Scott Blvd., Santa Clara, CA 95054.Google Scholar