SPARC: An ASIC Solution for High-Performance Microprocessors
Sun Microsystems’ Scalable Processor Architecture (SPARC) defines a general purpose 32-bit processor architecture. It was designed to allow cost effective and high performance implementations across a range of technologies. The simple yet efficient nature of the architecture makes it possible to implement it in a short period of time. It also makes SPARC very attractive for implementation in ASIC technologies, without sacrificing high performance. Its first implementation has been done in Fujitsu’s C20K gate array, and is the first high performance microprocessor to be designed in an ASIC technology. This paper summarizes the architecture and its gate array implementation.
Sun Microsystems is working towards making SPARC a truly open, multi-vendor processor architecture. It has already been licensed to three semiconductor companies: Fujitsu Microelectronics, Cypress Semiconductor and Bipolar Integrated Technology. A number of system houses including AT&T and Xerox have announced their intent to use SPARC in future products. In addition, the semiconductor licensees have had a number of design wins.
KeywordsRegister File Program Counter Register Window ASIC Technology Integer Unit
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