Abstract
This paper presents an overview of the first two implementations of Sun Microsystem’s Scalable Processor ARChitecture (SPARC). The first implementation, MB86900, is designed using a 20,000 gate 1.3 micron CMOS gate-array from Fujitsu. It operates at a clock rate of 16.6 MHz and delivers an average performance of 10 integer MIPS. The second, CY7C601, is a full custom chip designed using Cypress Semiconductor’s 0.8 micron CMOS process. It operates at a clock rate of 33 MHz and delivers an average performance of 20 integer MIPS. In this paper we discuss the basic features of these processors, their similarities and differences and the tradeoffs used in their design. We also address the issues of design verification, test generation and fault simulation.
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References
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© 1991 Sun Microsystems, Inc.
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Namjoo, M. (1991). First 32-Bit SPARC-Based Processors Implemented in High-Speed CMOS. In: Catanzaro, B.J. (eds) The SPARC Technical Papers. Sun Technical Reference Library. Springer, New York, NY. https://doi.org/10.1007/978-1-4612-3192-9_7
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DOI: https://doi.org/10.1007/978-1-4612-3192-9_7
Publisher Name: Springer, New York, NY
Print ISBN: 978-0-387-97634-1
Online ISBN: 978-1-4612-3192-9
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