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Implementation on RISC Architectures

  • Richard Tolimieri
  • Myoung An
  • Chao Lu
Part of the Signal Processing and Digital Filtering book series (SIGNAL PROCESS)

Abstract

A wide variety of DFT and convolution algorithms have been designed to optimize computations with respect to the number of arithmetic operations, especially multiplications. Blahut (1985) [1]offers an excellent survey of many algorithms designed using this methodology. Today, with the rapid advance in VLSI technology and the availability of high-speed and inexpensive floating-point processors, the time required to carry out a fixed-point addressing operation or a floating-point addition can effectively be the same as that for the floating-point multiplication. Some advanced architectures have these functional units working in parallel, with multiple operations realized in one or a few cycles at the same time. Traditional algorithm design of trading multiplications for additions, therefore, is not only ineffective but can result in a significant decrease in performance.

Keywords

Discrete Fourier Transform Data Cache Assembly Code Intel I860 Machine Cycle 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1997

Authors and Affiliations

  • Richard Tolimieri
    • 1
  • Myoung An
    • 2
  • Chao Lu
    • 3
  1. 1.Department of Electrical EngineeringCity College of CUNYNew YorkUSA
  2. 2.A.J. Devaney AssociatesAllstonUSA
  3. 3.Department of Computer and Information SciencesTowson State UniversityTowsonUSA

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