Simulation and modeling of updrain TMOS devices

Abstract

Updrain TMOS devices are well-known for the on-chip realization of switches in automotive power applications. Such devices are built up from many individual TMOS-cells, whose drain contact is connected to the drain pad via a buried-layer system, an updrain sinker and the metal layers of the chip. Because of the rather high resistance of the buried layer and the thin structure of the metal layers, interconnection voltage drops occur during on-state device operation, which can strongly reduce the externally applied source to drain voltage. Furthermore the high density of power-dissipation leads to heating effects, which can change the device behaviour remarkably. It is therefore one of the most important questions for designers working on smart power applications, how to achieve an effective layout with minimum on-resistance and less pronounced temperature effects. On August 2, 1996 Rainer Thoma from Motorola presented recent work on the decoupled electrical and thermal problems of TMOS devices. He discussed numerical results and then went on to derive analytical models based on a system of differential equations for the electrostatic potentials. He concluded with open problems regarding the optimization of the device layout.