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VLSI Programming of Asynchronous Circuits for Low Power

  • Kees van Berkel
  • Martin Rem
Part of the Workshops in Computing book series (WORKSHOPS COMP.)

Abstract

In this chapter we analyze the potential of asynchronous circuits for low power consumption. We set out by reviewing the mechanisms of energy dissipation of digital CMOS ICs in general and clocked circuits in particular. For many applications the generation and distribution of the clock signal account for more than half the power dissipation, directly or indirectly. Much of this wasted clock power — and often much more — can be saved by applying asynchronous circuit techniques.

This will be illustrated by a variety of simple, but practical examples: N-fold repeaters, modulo-N counters, ripple and wagging implementations of shift registers, ±2 M -incrementers, parallel-to-serial converters, and systolic computations.

We apply a programming approach to the design of these circuits using the CSP-based VLSI-programming language Tangram. So-called handshake circuits form an intermediate architecture between Tangram and asynchronous circuits. The transparent compilation of Tangram enables a simple analysis of power, performance, and costs of generated VLSI circuits. This method has been applied to several industrial applications, including a 2-IC realization of a DCC error corrector comprising 155 k transistors.

Keywords

Time Slot Power Dissipation CMOS Circuit Head Cell Asynchronous Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag London 1995

Authors and Affiliations

  • Kees van Berkel
    • 1
  • Martin Rem
    • 2
  1. 1.Philips Research Laboratories, WAY4EindhovenThe Netherlands
  2. 2.Eindhoven University of TechnologyEindhovenThe Netherlands

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