Using Transformations and Verification in Circuit Design

  • James B. Saxe
  • James J. Horning
  • John V. Guttag
  • Stephen J. Garland
Conference paper
Part of the Workshops in Computing book series (WORKSHOPS COMP.)


We show how machine-checked verification can support an approach to circuit design based on transformations. This approach starts with a conceptually simple (but inefficient) initial design and uses a combination of ad hoc and algorithmic transformations to produce a design that is more efficient (but more complex).

We present an example in which we start with a simplified CPU design and derive an efficient pipelined form, including circuitry for reverting the effects of partially executed instructions when a successful branch is detected late in the pipeline. The algorithmic stage of our derivation applies a transformation, retiming, that has been proven to preserve functional behavior in the general case. The ad hoc stage requires special justification, which we supply in the form of a machine-checked formal verification.


Clock Cycle Data Path Register File Formal Verification Combinational Logic 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag London 1993

Authors and Affiliations

  • James B. Saxe
    • 1
  • James J. Horning
    • 1
  • John V. Guttag
    • 2
  • Stephen J. Garland
    • 2
  1. 1.Systems Research CenterDigital Equipment CorporationPalo AltoUSA
  2. 2.Laboratory for Computer ScienceMassachusetts Institute of TechnologyCambridgeUSA

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