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Optimising designs by transposition

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Designing Correct Circuits

Part of the book series: Workshops in Computing ((WORKSHOPS COMP.))

Abstract

The purpose of this paper is fourfold: first, to describe some observations about how array-based designs can be optimised by transposition — a method of rearranging components and their interconnections; second, to provide concise parametric representations of such designs; third, to present simple equations that correspond to correctness-preserving transformations of these parametric representations; and finally, to suggest quantitative measures of design trade-offs involved in this kind of transformation.

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References

  1. G. Jones and M. Sheeran, Timeless truths about sequential circuits., in S. K. Tewks-bury, B. W. Dickinson and S. C. Schwartz (eds.), Concurrent computations: algorithms, architectures and technology., pp. 245–259, Plenum Press, 1988.

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  2. G. Jones and M. Sheeran, Circuit design in Ruby., in J. Staunstrup (ed.), Formal methods for VLSI design., North-Holland, 1990.

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  3. W. Luk, Specifying and developing regular heterogeneous designs., in L. Claesen (ed.), Formal VLSI specification and synthesis., pp. 391–409, North-Holland, 1990.

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  4. W. Luk and G. Jones, The derivation of regular synchronous circuits., in K. Bromley, S. Y. Kung and E. Swartzlander (eds.), Proceedings of International Conference on systolic arrays., pp. 305–314, IEEE Computer Society Press, 1988.

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  5. J. Moreno and T. Lang, On Partitioning the Faddeev algorithm., in K. Bromley, S. Y. Kung and E. Swartzlander (eds.), Proceedings of International Conference on systolic arrays., pp. 125–134, IEEE Computer Society Press, 1988.

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  6. L. Rossen, HOL formalisation of Ruby., Technical Report ID-TR 1989–61, Department of Computer Science, Technical University of Denmark, 1989.

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  7. S. Singh, An application of non-standard interpretation: testability., in L. Claesen (ed.), Formal VLSI correctness verification., pp. 235–244, North-Holland, 1990.

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© 1991 Springer-Verlag London

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Luk, W. (1991). Optimising designs by transposition. In: Jones, G., Sheeran, M. (eds) Designing Correct Circuits. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3544-9_18

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  • DOI: https://doi.org/10.1007/978-1-4471-3544-9_18

  • Publisher Name: Springer, London

  • Print ISBN: 978-3-540-19659-4

  • Online ISBN: 978-1-4471-3544-9

  • eBook Packages: Springer Book Archive

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