Serial Distributed Sample Scrambling
In the distributed sample scrambling (DSS), which is identical to the FSS in the scrambling and descrambling operations, the descrambler SRG is synchronized to the scrambler SRG using the transmitted samples of the scrambling sequence. In this chapter, we consider the synchronization process of the serial DSS and examine how to realize the scramblers and the descramblers. For this, we first mathematically model the synchronization process along with the scrambler and descrambler SRGs. Then, for the scramblers we consider how to determine the scrambler SRGs and how to sample the scrambling sequence; and for the descramblers we consider how to determine the descrambler SRGs and how to use the samples for the synchronization, along with their efficient realization methods. Finally, we consider how to design the DSS without employing complex timing circuitry.
KeywordsSampling Time State Vector Space Versus Generate Vector Correction Process
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