Parallel Computations and Delay-Insensitive Circuits

  • Jo C. Ebergen
Conference paper
Part of the Workshops in Computing book series (WORKSHOPS COMP.)

Abstract

Delay-insensitive circuits are attractive implementations for parallel computations. A delay-insensitive circuit is a special type of asynchronous circuit and can informally be characterised as a network of components of which the correctness is insensitive to delays in basic components and connection wires. The principles underlying the design of delay-insensitive circuits are explained. By means of a few examples we illustrate how parallel computations can be expressed conveniently in a simple program notation. In particular the design of the proper synchronisation among the subcomputations is illustrated. Subsequently, we show how such a program can be transformed into a delay-insensitive circuit and how timing problems can be avoided in implementing the synchronisations.

Keywords

Europe Prefix Guaran 

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Copyright information

© British Computer Society 1991

Authors and Affiliations

  • Jo C. Ebergen
    • 1
  1. 1.Computer Science DepartmentUniversity of WaterlooWaterlooCanada

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