Abstract
Delay-insensitive circuits are attractive implementations for parallel computations. A delay-insensitive circuit is a special type of asynchronous circuit and can informally be characterised as a network of components of which the correctness is insensitive to delays in basic components and connection wires. The principles underlying the design of delay-insensitive circuits are explained. By means of a few examples we illustrate how parallel computations can be expressed conveniently in a simple program notation. In particular the design of the proper synchronisation among the subcomputations is illustrated. Subsequently, we show how such a program can be transformed into a delay-insensitive circuit and how timing problems can be avoided in implementing the synchronisations.
This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP0041920.
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© 1991 British Computer Society
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Ebergen, J.C. (1991). Parallel Computations and Delay-Insensitive Circuits. In: Birtwistle, G. (eds) IV Higher Order Workshop, Banff 1990. Workshops in Computing. Springer, London. https://doi.org/10.1007/978-1-4471-3182-3_7
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DOI: https://doi.org/10.1007/978-1-4471-3182-3_7
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