Parallel Computations and Delay-Insensitive Circuits

  • Jo C. Ebergen
Part of the Workshops in Computing book series (WORKSHOPS COMP.)


Delay-insensitive circuits are attractive implementations for parallel computations. A delay-insensitive circuit is a special type of asynchronous circuit and can informally be characterised as a network of components of which the correctness is insensitive to delays in basic components and connection wires. The principles underlying the design of delay-insensitive circuits are explained. By means of a few examples we illustrate how parallel computations can be expressed conveniently in a simple program notation. In particular the design of the proper synchronisation among the subcomputations is illustrated. Subsequently, we show how such a program can be transformed into a delay-insensitive circuit and how timing problems can be avoided in implementing the synchronisations.


Communication Behaviour Mutual Exclusion Asynchronous Circuit Program Notation Primitive Component 
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  1. [1]
    J.A. Brzozowski and J.C. Ebergen, Recent Developments in the Design of Asynchronous Circuits, Proc. Fundamentals of Computation Theory–FCT’89, J. Csirik, J. Demetrovics, F. Gecség (eds), Lecture Notes in Computer Science, vol. 380, ( Springer-Verlag, Berlin, 1989 ), 78–95.Google Scholar
  2. [2]
    T.J. Chaney and C.E. Molnar, Anomalous Behavior of Synchronizer and Arbiter Circuits, IEEE Transactions on Computers, (C-22), (1973), 421–422.CrossRefGoogle Scholar
  3. [3]
    W. Chen, J.T. Udding, and T. Verhoeff, Networks of Communicating Processes and Their (De-)Composition, in: J.L.A. van de Snepscheut (ed), Mathematics of Program Construction, Lecture Notes in Computer Science 375, (Springer-Verlag, 1989 ), 174–196.Google Scholar
  4. [4]
    D.L. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits, (MIT Press, 1989 ).Google Scholar
  5. [5]
    David L. Dill, Steven M. Nowick, and Robert F. Sproull, Automatic Verification of Speed-independent Circuits with Petri Net Specifications, Proc. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, (IEEE Computer Society, 1989 ), 212–216.Google Scholar
  6. [6]
    Jo C. Ebergen, Translating Programs into Delay-Insensitive Circuits, CWI Tract 56, ( Centre for Mathematics and Computing Science, Amsterdam, 1989 ).Google Scholar
  7. [7]
    Jo C. Ebergen, Arbiters: An Exercise in Specifying and Decomposing Asynchronously Communicating Components, Technical Report CS-90–29, Department of Computer Science, University of Waterloo, (1990).Google Scholar
  8. [8]
    C.A.R. Hoare, Communicating Sequential Processes, (Prentice-Hall, 1985 ).Google Scholar
  9. [9]
    A.J. Martin, Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits, in: C.A.R. Hoare (ed), UT Year of Programming Institute on Concurrent Programming, (Addison-Wesley, 1989 ).Google Scholar
  10. [10]
    C.E. Molnar, T.P. Fang and F.U. Rosenberger, Synthesis of Delay-Insensitive Modules, in: H. Fuchs (ed), Proceedings 1985 Chapel Hill Conference on VLSI, (Computer Science Press, 1985 ), 67–86.Google Scholar
  11. [11]
    M. Rem, The Nature of Delay-Insensitive Computing, in these proceedings.Google Scholar
  12. [12]
    M. Rem, Trace Theory and Systolic Computations, in: J.W. de Bakker, A.J. Nijman and P.C. Treleaven (eds), Proceedings PARLE, Parallel Architectures and Languages Europe, Vol. 1, (Springer-Verlag, 1987 ), 14–34.Google Scholar
  13. [13]
    C.L. Seitz, System Timing, in: Carver Mead and Lynn Conway (eds), Introduction to VLSI Systems, (Addison-Wesley, 1980 ), 218–262.Google Scholar
  14. [14]
    I.E. Sutherland, Micropipelines, Communications of the ACM, (32) 6, (1989), 720–738.CrossRefGoogle Scholar
  15. [15]
    J.T. Udding, A Formal Model for Defining and Classifying Delay-Insensitive Circuits and Systems, Distributed Computing, (1), (1986), 197–204.CrossRefGoogle Scholar
  16. [16]
    C. van Berkel, C. Niessen, M. Rem, and R. Saeijs, VLSI Programming and Silicon Compilation: a Novel Approach from Philips Research, in: Proceedings of IEEE International Conference on Computer Design 1988, (1988).Google Scholar
  17. [17]
    J.L.A. van de Snepscheut, Trace Theory and VLSI Design,Lecture Notes in Computer Science 200, (Springer-Verlag, 1985).Google Scholar

Copyright information

© British Computer Society 1991

Authors and Affiliations

  • Jo C. Ebergen
    • 1
  1. 1.Computer Science DepartmentUniversity of WaterlooWaterlooCanada

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